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Revision 1.221.2.1.2.1 / (download) - annotate - [select for diffs], Fri Nov 11 04:20:22 2011 UTC (3 months ago) by kensmith
Branch: RELENG_9_0
CVS Tags: RELENG_9_0_0_RELEASE
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SVN rev 227445 on 2011-11-11 04:20:22Z by kensmith Copy stable/9 to releng/9.0 as part of the FreeBSD 9.0-RELEASE release cycle. Approved by: re (implicit)
Revision 1.221.2.1 / (download) - annotate - [select for diffs], Fri Sep 23 00:51:37 2011 UTC (4 months, 2 weeks ago) by kensmith
Branch: RELENG_9
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SVN rev 225736 on 2011-09-23 00:51:37Z by kensmith Copy head to stable/9 as part of 9.0-RELEASE release cycle. Approved by: re (implicit)
Revision 1.202.2.12 / (download) - annotate - [select for diffs], Fri May 20 22:38:02 2011 UTC (8 months, 3 weeks ago) by jkim
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SVN rev 222153 on 2011-05-20 22:38:02Z by jkim MFC: r222043 Update CPUID bits to reflect AMD Bulldozer and Intel Sandy Bridge features.
Revision 1.180.2.17 / (download) - annotate - [select for diffs], Fri May 20 22:24:26 2011 UTC (8 months, 3 weeks ago) by jkim
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SVN rev 222151 on 2011-05-20 22:24:26Z by jkim MFC: r221188 Define "Hypervisor Present" bit. This bit is used by several hypervisors to identify CPUs running under emulation.
Revision 1.202.2.11 / (download) - annotate - [select for diffs], Fri May 20 22:22:56 2011 UTC (8 months, 3 weeks ago) by jkim
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SVN rev 222150 on 2011-05-20 22:22:56Z by jkim MFC: r221188 Define "Hypervisor Present" bit. This bit is used by several hypervisors to identify CPUs running under emulation.
Revision 1.221 / (download) - annotate - [select for diffs], Tue May 17 22:36:16 2011 UTC (8 months, 3 weeks ago) by jkim
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SVN rev 222043 on 2011-05-17 22:36:16Z by jkim Update CPUID bits to reflect AMD Bulldozer and Intel Sandy Bridge features. Note AMD dropped SSE5 extensions in order to avoid ISA overlap with Intel AVX instructions. The SSE5 bit was recycled as XOP extended instruction bit, CVT16 was deprecated in favor of F16C (half-precision float conversion instructions for AVX), and the remaining FMA4 (4-operand FMA instructions) gained a separate CPUID bit. Replace non-existent references with today's CPUID specifications.
Revision 1.220 / (download) - annotate - [select for diffs], Thu Apr 28 22:23:39 2011 UTC (9 months, 2 weeks ago) by jkim
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SVN rev 221188 on 2011-04-28 22:23:39Z by jkim Define "Hypervisor Present" bit. This bit is used by several hypervisors to identify CPUs running under emulation. Currently QEMU-KVM, Xen-HVM, VMware, and MS Hyper-V are known to set this bit. MFC after: 3 days
Revision 1.219 / (download) - annotate - [select for diffs], Tue Apr 12 22:15:46 2011 UTC (10 months ago) by jkim
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SVN rev 220579 on 2011-04-12 22:15:46Z by jkim Probe capability to find effective frequency. When the TSC is P-state invariant, APERF/MPERF ratio can be used to find effective frequency.
Revision 1.218 / (download) - annotate - [select for diffs], Sat Mar 26 02:02:07 2011 UTC (10 months, 2 weeks ago) by jkim
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SVN rev 220018 on 2011-03-26 02:02:07Z by jkim Improve CPU identifications of various IDT/Centaur/VIA, Rise and Transmeta CPUs. These CPUs need explicit MSR configuration to expose ceratin CPU capabilities (e.g., CMPXCHG8B) to work around compatibility issues with ancient software. Unfortunately, Rise mP6 does not set the CX8 bit in CPUID and there is no MSR to expose the feature although all mP6 processors are capable of CMPXCHG8B according to datasheets I found from the Net. Clean up and simplify VIA PadLock detection while I am in the neighborhood.
Revision 1.217 / (download) - annotate - [select for diffs], Thu Mar 10 22:20:11 2011 UTC (11 months ago) by jkim
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SVN rev 219467 on 2011-03-10 22:20:11Z by jkim Detect NSC/AMD Geode SC1100 properly, not just Stepping 0. Although it is unclear that "TSC stops ticking with HLT instruction" problem is present with other steppings, it is limited to Stepping 0 for now.
Revision 1.216 / (download) - annotate - [select for diffs], Thu Mar 10 20:02:58 2011 UTC (11 months ago) by jkim
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SVN rev 219461 on 2011-03-10 20:02:58Z by jkim Deprecate rarely used tsc_is_broken. Instead, we zero out tsc_freq because it is almost always used with tsc_freq any way.
Revision 1.180.2.16.2.1 / (download) - annotate - [select for diffs], Tue Dec 21 17:10:29 2010 UTC (13 months, 3 weeks ago) by kensmith
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SVN rev 216618 on 2010-12-21 17:10:29Z by kensmith Copy stable/7 to releng/7.4 in preparation for FreeBSD-7.4 release. Approved by: re (implicit)
Revision 1.202.2.10.2.1 / (download) - annotate - [select for diffs], Tue Dec 21 17:09:25 2010 UTC (13 months, 3 weeks ago) by kensmith
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SVN rev 216617 on 2010-12-21 17:09:25Z by kensmith Copy stable/8 to releng/8.2 in preparation for FreeBSD-8.2 release. Approved by: re (implicit)
Revision 1.215 / (download) - annotate - [select for diffs], Tue Dec 7 22:43:25 2010 UTC (14 months ago) by jkim
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SVN rev 216276 on 2010-12-07 22:43:25Z by jkim Remove stale comments about P-state invariant TSC and fix style(9) nits.
Revision 1.214 / (download) - annotate - [select for diffs], Tue Dec 7 22:34:51 2010 UTC (14 months ago) by jkim
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SVN rev 216275 on 2010-12-07 22:34:51Z by jkim Do not register a event handler for CPU freqency changes when it is found P-state invariant. This is continuation of r216274.
Revision 1.213 / (download) - annotate - [select for diffs], Tue Dec 7 22:12:02 2010 UTC (14 months ago) by jkim
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SVN rev 216272 on 2010-12-07 22:12:02Z by jkim Probe P-state invariant TSC from rightful place.
Revision 1.202.2.10 / (download) - annotate - [select for diffs], Fri Nov 19 09:49:14 2010 UTC (14 months, 3 weeks ago) by kib
Branch: RELENG_8
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SVN rev 215513 on 2010-11-19 09:49:14Z by kib
Merge the kern_fpu_enter/kern_fpu_leave KPI and followup fixes for the
amd64 suspend/resume support.
Tested by: Mike Tancsa
Also tested by: Dewayne Geraghty <dewayne.geraghty heuristicsystems com au>,
Daryl Richards <daryl isletech net>
Below is the svn log of the merged revisions.
------------------------------------------------------------------------
r197455 | emaste | 2009-09-24 17:26:42 +0300 (Thu, 24 Sep 2009) | 5 lines
Add a backtrace to the "fpudna in kernel mode!" case, to help track down
where this comes from.
Reviewed by: bde
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r197863 | jkim | 2009-10-08 20:41:53 +0300 (Thu, 08 Oct 2009) | 8 lines
Clean up amd64 suspend/resume code.
- Allocate memory for wakeup code after ACPI bus is attached. The early
memory allocation hack was inherited from i386 but amd64 does not need it.
- Exclude real mode IVT and BDA explicitly. Improve comments about memory
allocation and reason for the exclusions. It is a no-op in reality, though.
- Remove an unnecessary CLD from wakeup code and re-align.
------------------------------------------------------------------------
r198931 | jkim | 2009-11-05 00:39:18 +0200 (Thu, 05 Nov 2009) | 2 lines
Tweak memory allocation for amd64 suspend/resume CPU context.
------------------------------------------------------------------------
r200280 | jkim | 2009-12-09 00:38:42 +0200 (Wed, 09 Dec 2009) | 2 lines
Simplify a macro not to generate unncessary symbols.
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r205444 | emaste | 2010-03-22 13:52:53 +0200 (Mon, 22 Mar 2010) | 7 lines
Merge r197455 from amd64:
Add a backtrace to the "fpudna in kernel mode!" case, to help track down
where this comes from.
Reviewed by: bde
------------------------------------------------------------------------
r208833 | kib | 2010-06-05 18:59:59 +0300 (Sat, 05 Jun 2010) | 15 lines
Introduce the x86 kernel interfaces to allow kernel code to use
FPU/SSE hardware. Caller should provide a save area that is chained
into the stack of the areas; pcb save_area for usermode FPU state is
on top. The pcb now contains a pointer to the current FPU saved area,
used during FPUDNA handling and context switches. There is also a
facility to allow the kernel thread to use pcb save_area.
Change the dreaded warnings "npxdna in kernel mode!" into the panics
when FPU usage is not registered.
KPI discussed with: fabient
Tested by: pho, fabient
Hardware provided by: Sentex Communications
MFC after: 1 month
------------------------------------------------------------------------
r208834 | kib | 2010-06-05 19:00:53 +0300 (Sat, 05 Jun 2010) | 13 lines
Use the fpu_kern_enter() interface to properly separate usermode FPU
context from in-kernel execution of padlock instructions and to handle
spurious FPUDNA exceptions that sometime are raised when doing padlock
calculations.
Globally mark crypto(9) kthread as using FPU.
Reviewed by: pjd
Hardware provided by: Sentex Communications
Tested by: pho
PR: amd64/135014
MFC after: 1 month
------------------------------------------------------------------------
r208877 | kib | 2010-06-06 19:13:50 +0300 (Sun, 06 Jun 2010) | 5 lines
Style-compilant order of declarations.
Noted by: bde
MFC after: 1 month
------------------------------------------------------------------------
r209174 | jkim | 2010-06-14 23:08:26 +0300 (Mon, 14 Jun 2010) | 3 lines
Fix ACPI suspend/resume on amd64, which was broken since r208833.
We need actual storage for FPU state to save and restore.
------------------------------------------------------------------------
r209198 | kib | 2010-06-15 12:19:33 +0300 (Tue, 15 Jun 2010) | 10 lines
Use critical sections instead of disabling local interrupts to ensure
the consistency between PCPU fpcurthread and the state of the FPU.
Explicitely assert that the calling conventions for fpudrop() are
adhered too. In cpu_thread_exit(), add missed critical section entrance.
Reviewed by: bde
Tested by: pho
MFC after: 1 month
------------------------------------------------------------------------
r209204 | kib | 2010-06-15 17:59:35 +0300 (Tue, 15 Jun 2010) | 5 lines
Rename CRITSECT_ASSERT to CRITICAL_ASSERT.
Suggested by: jhb
MFC after: 1 month
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r209208 | kib | 2010-06-15 21:16:04 +0300 (Tue, 15 Jun 2010) | 4 lines
Remove two obsoleted comments, add a note about 32bit compatibility.
MFC after: 1 month
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r209252 | kib | 2010-06-17 15:35:17 +0300 (Thu, 17 Jun 2010) | 6 lines
In the ia32_{get,set}_fpcontext(), use fpu{get,set}userregs instead
of fpu{get,set}regs.
Noted by: bde
MFC after: 1 month
------------------------------------------------------------------------
r209460 | kib | 2010-06-23 13:40:28 +0300 (Wed, 23 Jun 2010) | 8 lines
Remove unused i586 optimized bcopy/bzero/etc implementations that utilize
FPU registers for copying. Remove the switch table and jumps from
bcopy/bzero/... to the actual implementation.
As a side-effect, i486-optimized bzero is removed.
Reviewed by: bde
Tested by: pho (previous version)
------------------------------------------------------------------------
r209461 | kib | 2010-06-23 14:12:58 +0300 (Wed, 23 Jun 2010) | 8 lines
Remove the support for int13 FPU exception reporting on i386. It is
believed that all 486-class CPUs FreeBSD is capable to run on, either
have no FPU and cannot use external coprocessor, or have FPU on the
package and can use #MF.
Reviewed by: bde
Tested by: pho (previous version)
------------------------------------------------------------------------
r209462 | kib | 2010-06-23 14:21:19 +0300 (Wed, 23 Jun 2010) | 8 lines
After the FPU use requires #MF working due to INT13 FPU exception handling
removal, MFi386 r209198:
Use critical sections instead of disabling local interrupts to ensure
the consistency between PCPU fpcurthread and the state of FPU.
Reviewed by: bde
Tested by: pho
------------------------------------------------------------------------
r210514 | jkim | 2010-07-26 22:53:09 +0300 (Mon, 26 Jul 2010) | 6 lines
Re-implement FPU suspend/resume for amd64. This removes superfluous uses
of critical_enter(9) and critical_exit(9) by fpugetregs() and fpusetregs().
Also, we do not touch PCB flags any more.
MFC after: 1 month
------------------------------------------------------------------------
r210517 | jkim | 2010-07-27 00:24:52 +0300 (Tue, 27 Jul 2010) | 4 lines
FNSTSW instruction can use AX register as an operand.
Obtained from: fenv.h
------------------------------------------------------------------------
r210518 | jkim | 2010-07-27 01:16:36 +0300 (Tue, 27 Jul 2010) | 5 lines
Reduce diff against fenv.h:
Mark all inline asms as volatile for safety. No object file change after
this commit (verified with md5).
------------------------------------------------------------------------
r210519 | jkim | 2010-07-27 01:55:14 +0300 (Tue, 27 Jul 2010) | 2 lines
Remove an unused macro since r189418.
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r210520 | jkim | 2010-07-27 02:02:18 +0300 (Tue, 27 Jul 2010) | 2 lines
Add missing ldmxcsr() prototype for lint case.
------------------------------------------------------------------------
r210521 | jkim | 2010-07-27 02:20:55 +0300 (Tue, 27 Jul 2010) | 3 lines
Simplify fldcw() macro. There is no reason to use pointer here. No object
file change after this commit (verified with md5).
------------------------------------------------------------------------
r210614 | jkim | 2010-07-29 19:41:21 +0300 (Thu, 29 Jul 2010) | 2 lines
Rename PCB_USER_FPU to PCB_USERFPU not to clash with a macro from fpu.h.
------------------------------------------------------------------------
r210615 | jkim | 2010-07-29 19:49:20 +0300 (Thu, 29 Jul 2010) | 5 lines
Fix another fallout from r208833. savectx() is used to save CPU context
for crash dump (dumppcb) and kdb (stoppcbs). For both cases, there cannot
have a valid pointer in pcb_save. This should restore the previous
behaviour.
------------------------------------------------------------------------
r210777 | jkim | 2010-08-02 20:35:00 +0300 (Mon, 02 Aug 2010) | 13 lines
- Merge savectx2() with savectx() and struct xpcb with struct pcb. [1]
savectx() is only used for panic dump (dumppcb) and kdb (stoppcbs). Thus,
saving additional information does not hurt and it may be even beneficial.
Unfortunately, struct pcb has grown larger to accommodate more data.
Move 512-byte long pcb_user_save to the end of struct pcb while I am here.
- savectx() now saves FPU state unconditionally and copy it to the PCB of
FPU thread if necessary. This gives panic dump and kdb a chance to take
a look at the current FPU state even if the FPU is "supposedly" not used.
- Resuming CPU now unconditionally reinitializes FPU. If the saved FPU
state was irrelevant, it could be in an unknown state.
Suggested by: bde [1]
------------------------------------------------------------------------
r210804 | jkim | 2010-08-03 18:32:08 +0300 (Tue, 03 Aug 2010) | 6 lines
savectx() has not been used for fork(2) for about 15 years. [1]
Do not clobber FPU thread's PCB as it is more harmful. When we resume CPU,
unconditionally reload FPU state.
Pointed out by: bde [1]
------------------------------------------------------------------------
r212026 | jkim | 2010-08-31 00:19:42 +0300 (Tue, 31 Aug 2010) | 3 lines
Save MSR_FSBASE, MSR_GSBASE and MSR_KGSBASE directly to PCB as we do not use
these values in the function.
------------------------------------------------------------------------
r214347 | jhb | 2010-10-25 18:31:13 +0300 (Mon, 25 Oct 2010) | 5 lines
Use 'saveintr' instead of 'savecrit' or 'eflags' to hold the state returned
by intr_disable().
Requested by: bde
------------------------------------------------------------------------
Revision 1.202.2.9 / (download) - annotate - [select for diffs], Tue Nov 9 18:43:59 2010 UTC (15 months ago) by jhb
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SVN rev 215043 on 2010-11-09 18:43:59Z by jhb MFC 214346: Use intr_disable() and intr_restore() instead of frobbing the flags register directly to disable interrupts.
Revision 1.212 / (download) - annotate - [select for diffs], Mon Oct 25 15:28:03 2010 UTC (15 months, 2 weeks ago) by jhb
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SVN rev 214346 on 2010-10-25 15:28:03Z by jhb Use intr_disable() and intr_restore() instead of frobbing the flags register directly to disable interrupts. Reviewed by: bde (earlier version) MFC after: 2 weeks
Revision 1.202.2.8 / (download) - annotate - [select for diffs], Tue Oct 12 09:10:24 2010 UTC (16 months ago) by kib
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SVN rev 213715 on 2010-10-12 09:10:24Z by kib MFC r213452: Display PCID capability of CPU and add CPUID define for it.
Revision 1.211 / (download) - annotate - [select for diffs], Tue Oct 5 15:31:56 2010 UTC (16 months ago) by kib
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SVN rev 213452 on 2010-10-05 15:31:56Z by kib Display PCID capability of CPU and add CPUID define for it. MFC after: 1 week
Revision 1.210 / (download) - annotate - [select for diffs], Wed Jun 23 10:40:28 2010 UTC (19 months, 2 weeks ago) by kib
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SVN rev 209460 on 2010-06-23 10:40:28Z by kib Remove unused i586 optimized bcopy/bzero/etc implementations that utilize FPU registers for copying. Remove the switch table and jumps from bcopy/bzero/... to the actual implementation. As a side-effect, i486-optimized bzero is removed. Reviewed by: bde Tested by: pho (previous version)
Revision 1.202.2.7.2.1 / (download) - annotate - [select for diffs], Mon Jun 14 02:09:06 2010 UTC (19 months, 4 weeks ago) by kensmith
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SVN rev 209145 on 2010-06-14 02:09:06Z by kensmith Copy stable/8 to releng/8.1 in preparation for 8.1-RC1. Approved by: re (implicit)
Revision 1.202.2.7 / (download) - annotate - [select for diffs], Wed May 12 09:34:10 2010 UTC (21 months ago) by kib
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SVN rev 207955 on 2010-05-12 09:34:10Z by kib MFC r207676: Add definitions for Intel AESNI CPUID bits and print the capabilities on boot.
Revision 1.209 / (download) - annotate - [select for diffs], Wed May 5 21:07:47 2010 UTC (21 months, 1 week ago) by kib
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SVN rev 207676 on 2010-05-05 21:07:47Z by kib Add definitions for Intel AESNI CPUID bits and print the capabilities on boot. Hardware provided by: Sentex Communications MFC after: 1 week
Revision 1.180.2.16 / (download) - annotate - [select for diffs], Thu Mar 25 15:53:02 2010 UTC (22 months, 2 weeks ago) by jhb
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SVN rev 205646 on 2010-03-25 15:53:02Z by jhb MFC 205013: Print out the family and model from the cpu_id. This is especially useful given the advent of the extended family and extended model fields. The values are printed in hex to match their common usage in documentation.
Revision 1.202.2.6 / (download) - annotate - [select for diffs], Thu Mar 25 15:48:23 2010 UTC (22 months, 2 weeks ago) by jhb
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SVN rev 205645 on 2010-03-25 15:48:23Z by jhb MFC 205013: Print out the family and model from the cpu_id. This is especially useful given the advent of the extended family and extended model fields. The values are printed in hex to match their common usage in documentation.
Revision 1.208 / (download) - annotate - [select for diffs], Thu Mar 11 14:17:37 2010 UTC (23 months ago) by jhb
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SVN rev 205013 on 2010-03-11 14:17:37Z by jhb Print out the family and model from the cpu_id. This is especially useful given the advent of the extended family and extended model fields. The values are printed in hex to match their common usage in documentation. Submitted by: Alexander Best MFC after: 1 week
Revision 1.180.2.15.2.1 / (download) - annotate - [select for diffs], Wed Feb 10 00:26:20 2010 UTC (2 years ago) by kensmith
Branch: RELENG_7_3
CVS Tags: RELENG_7_3_0_RELEASE
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SVN rev 203736 on 2010-02-10 00:26:20Z by kensmith Copy stable/7 to releng/7.3 as part of the 7.3-RELEASE process. Approved by: re (implicit)
Revision 1.180.2.15 / (download) - annotate - [select for diffs], Sun Dec 20 01:00:41 2009 UTC (2 years, 1 month ago) by avg
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SVN rev 200742 on 2009-12-20 01:00:41Z by avg MFC r197070: Consolidate CPUID to CPU family/model macros for amd64 and i386 This is to fix breakage caused by r200064. I do this MFC instead of just fixing r200064 to reduce difference from head and make things easier for future MFCs. Original change is by jkim. Pointy hat to: avg
Revision 1.180.2.14 / (download) - annotate - [select for diffs], Tue Dec 8 15:29:12 2009 UTC (2 years, 2 months ago) by avg
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SVN rev 200263 on 2009-12-08 15:29:12Z by avg MFC r199968: x86 cpu features: add MOVBE reporting and flag
Revision 1.202.2.5 / (download) - annotate - [select for diffs], Tue Dec 8 15:27:06 2009 UTC (2 years, 2 months ago) by avg
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SVN rev 200262 on 2009-12-08 15:27:06Z by avg MFC r199968: x86 cpu features: add MOVBE reporting and flag
Revision 1.207 / (download) - annotate - [select for diffs], Mon Nov 30 11:11:08 2009 UTC (2 years, 2 months ago) by avg
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SVN rev 199968 on 2009-11-30 11:11:08Z by avg x86 cpu features: add MOVBE reporting and flag The check is glimpsed from Linux and OpenSolaris. MOVBE instruction is found in Intel Atom processors.
Revision 1.145.2.8 / (download) - annotate - [select for diffs], Thu Nov 19 12:10:34 2009 UTC (2 years, 2 months ago) by nyan
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Diff to previous 1.145.2.7 (colored) to branchpoint 1.145 (colored) next main 1.146 (colored)
SVN rev 199521 on 2009-11-19 12:10:34Z by nyan MFC: revision 199219 Fix cpu model for PODP5V83. It is P24T, not P54T. Also remove redundant 'Overdrive' word.
Revision 1.180.2.13 / (download) - annotate - [select for diffs], Thu Nov 19 12:08:16 2009 UTC (2 years, 2 months ago) by nyan
Branch: RELENG_7
Changes since 1.180.2.12: +1 -1
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Diff to previous 1.180.2.12 (colored) to branchpoint 1.180 (colored)
SVN rev 199520 on 2009-11-19 12:08:16Z by nyan MFC: revision 199219 Fix cpu model for PODP5V83. It is P24T, not P54T. Also remove redundant 'Overdrive' word.
Revision 1.202.2.4 / (download) - annotate - [select for diffs], Thu Nov 19 12:07:00 2009 UTC (2 years, 2 months ago) by nyan
Branch: RELENG_8
Changes since 1.202.2.3: +1 -1
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Diff to previous 1.202.2.3 (colored) to branchpoint 1.202 (colored)
SVN rev 199519 on 2009-11-19 12:07:00Z by nyan MFC: revision 199219 Fix cpu model for PODP5V83. It is P24T, not P54T. Also remove redundant 'Overdrive' word.
Revision 1.206 / (download) - annotate - [select for diffs], Thu Nov 12 10:59:00 2009 UTC (2 years, 2 months ago) by nyan
Branch: MAIN
Changes since 1.205: +1 -1
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Diff to previous 1.205 (colored)
SVN rev 199219 on 2009-11-12 10:59:00Z by nyan Fix cpu model for PODP5V83. It is P24T, not P54T. Also remove redundant 'Overdrive' word. Pointed out by: SATOU Tomokazu (tomo1770 at maple ocn ne jp) MFC after: 1 week
Revision 1.202.2.1.2.3 / (download) - annotate - [select for diffs], Fri Nov 6 17:09:04 2009 UTC (2 years, 3 months ago) by attilio
Branch: RELENG_8_0
CVS Tags: RELENG_8_0_0_RELEASE
Changes since 1.202.2.1.2.2: +9 -9
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Diff to previous 1.202.2.1.2.2 (colored) to branchpoint 1.202.2.1 (colored) next main 1.202.2.2 (colored)
SVN rev 198991 on 2009-11-06 17:09:04Z by attilio MFC r197070: Consolidate CPUID to CPU family/model macros for amd64 and i386 to reduce unnecessary #ifdef's for shared code between them. This MFC should unbreak the kernel build breakage introduced by r198978. Reported by: kib Pointy hat to: me Approved by: re (kib)
Revision 1.202.2.3 / (download) - annotate - [select for diffs], Fri Nov 6 15:24:48 2009 UTC (2 years, 3 months ago) by attilio
Branch: RELENG_8
Changes since 1.202.2.2: +9 -9
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Diff to previous 1.202.2.2 (colored) to branchpoint 1.202 (colored)
SVN rev 198989 on 2009-11-06 15:24:48Z by attilio MFC r197070: Consolidate CPUID to CPU family/model macros for amd64 and i386 to reduce unnecessary #ifdef's for shared code between them. This MFC should unbreak the kernel build breakage introduced by r198977. Reported by: kib Pointy hat to: me
Revision 1.180.2.12 / (download) - annotate - [select for diffs], Fri Nov 6 10:38:33 2009 UTC (2 years, 3 months ago) by attilio
Branch: RELENG_7
Changes since 1.180.2.11: +15 -0
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Diff to previous 1.180.2.11 (colored) to branchpoint 1.180 (colored)
SVN rev 198979 on 2009-11-06 10:38:33Z by attilio MFC r198868, r198950: Opteron rev E family of processor expose a bug where acq memory barriers can be broken, resulting in random breakages. Printout a warning message if affected family and model are found.
Revision 1.202.2.1.2.2 / (download) - annotate - [select for diffs], Fri Nov 6 10:17:08 2009 UTC (2 years, 3 months ago) by attilio
Branch: RELENG_8_0
Changes since 1.202.2.1.2.1: +15 -0
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Diff to previous 1.202.2.1.2.1 (colored) to branchpoint 1.202.2.1 (colored)
SVN rev 198978 on 2009-11-06 10:17:08Z by attilio MFC r198868, r198950: Opteron rev E family of processor expose a bug where acq memory barriers can be broken, resulting in random breakages. Printout a warning message if affected family and model are found. Approved by: re (kib)
Revision 1.202.2.2 / (download) - annotate - [select for diffs], Fri Nov 6 10:15:15 2009 UTC (2 years, 3 months ago) by attilio
Branch: RELENG_8
Changes since 1.202.2.1: +15 -0
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Diff to previous 1.202.2.1 (colored) to branchpoint 1.202 (colored)
SVN rev 198977 on 2009-11-06 10:15:15Z by attilio MFC r198868, r198950: Opteron rev E family of processor expose a bug where acq memory barriers can be broken, resulting in random breakages. Printout a warning message if affecred family and model are found.
Revision 1.205 / (download) - annotate - [select for diffs], Thu Nov 5 14:34:38 2009 UTC (2 years, 3 months ago) by attilio
Branch: MAIN
Changes since 1.204: +1 -4
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Diff to previous 1.204 (colored)
SVN rev 198950 on 2009-11-05 14:34:38Z by attilio Strip from messages for users external URLs the project cannot directly control. Requested by: kib, rwatson
Revision 1.204 / (download) - annotate - [select for diffs], Wed Nov 4 01:32:59 2009 UTC (2 years, 3 months ago) by attilio
Branch: MAIN
Changes since 1.203: +18 -0
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Diff to previous 1.203 (colored)
SVN rev 198868 on 2009-11-04 01:32:59Z by attilio Opteron rev E family of processor expose a bug where, in very rare ocassions, memory barriers semantic is not honoured by the hardware itself. As a result, some random breakage can happen in uninvestigable ways (for further explanation see at the content of the commit itself). As long as just a specific familly is bugged of an entire architecture is broken, a complete fix-up is impratical without harming to some extents the other correct cases. Considering that (and considering the frequency of the bug exposure) just print out a warning message if the affected machine is identified. Pointed out by: Samy Al Bahra <sbahra at repnop dot org> Help on wordings by: jeff MFC: 3 days
Revision 1.202.2.1.2.1 / (download) - annotate - [select for diffs], Sun Oct 25 01:10:29 2009 UTC (2 years, 3 months ago) by kensmith
Branch: RELENG_8_0
Changes since 1.202.2.1: +0 -0
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SVN rev 198460 on 2009-10-25 01:10:29Z by kensmith Copy stable/8 to releng/8.0 as part of 8.0-RELEASE release procedure. Approved by: re (implicit)
Revision 1.203 / (download) - annotate - [select for diffs], Thu Sep 10 17:27:36 2009 UTC (2 years, 5 months ago) by jkim
Branch: MAIN
Changes since 1.202: +9 -9
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Diff to previous 1.202 (colored)
SVN rev 197070 on 2009-09-10 17:27:36Z by jkim Consolidate CPUID to CPU family/model macros for amd64 and i386 to reduce unnecessary #ifdef's for shared code between them.
Revision 1.202.2.1 / (download) - annotate - [select for diffs], Mon Aug 3 08:13:06 2009 UTC (2 years, 6 months ago) by kensmith
Branch: RELENG_8
CVS Tags: RELENG_8_0_BP
Branch point for: RELENG_8_0
Changes since 1.202: +0 -0
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Diff to previous 1.202 (colored)
SVN rev 196045 on 2009-08-03 08:13:06Z by kensmith Copy head to stable/8 as part of 8.0 Release cycle. Approved by: re (Implicit)
Revision 1.180.2.11 / (download) - annotate - [select for diffs], Tue Jul 14 18:40:31 2009 UTC (2 years, 6 months ago) by jkim
Branch: RELENG_7
Changes since 1.180.2.10: +18 -11
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Diff to previous 1.180.2.10 (colored) to branchpoint 1.180 (colored)
SVN rev 195687 on 2009-07-14 18:40:31Z by jkim MFC: r191788 Unlock the largest standard CPUID on Intel CPUs for both amd64 and i386. On i386, we extend it to cover Core, Core 2, and Core i7 processors, not just Pentium 4 family, and move it to better place. On amd64, all supported Intel CPUs should have this MSR.
Revision 1.180.2.10 / (download) - annotate - [select for diffs], Mon Jul 13 22:13:13 2009 UTC (2 years, 6 months ago) by jkim
Branch: RELENG_7
Changes since 1.180.2.9: +13 -2
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Diff to previous 1.180.2.9 (colored) to branchpoint 1.180 (colored)
SVN rev 195667 on 2009-07-13 22:13:13Z by jkim MFC: Replace remaining cpu_vendor with cpu_vendor_id and add basic VIA Nano processor support for amd64 and i386. r186797 - Add Centaur/IDT/VIA vendor ID for Nano family. r187101 - Allow VIA Nano processors to boot FreeBSD/amd64. r187117 - Replace more cpu_vendor with cpu_vendor_id. r187118 - Add basic i386 support for VIA Nano processors. r187157 - Enable MSI support for VIA Nano processors on i386. r187594 - Replace more cpu_vendor with cpu_vendor_id. r187597 - Include a missing header file. r187598 - VIA Nano processor has P-state invariant TSC. r187633 - Add more VIA bridges to agp_via.c.
Revision 1.180.2.9 / (download) - annotate - [select for diffs], Tue Jun 30 17:10:08 2009 UTC (2 years, 7 months ago) by avg
Branch: RELENG_7
Changes since 1.180.2.8: +81 -42
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Diff to previous 1.180.2.8 (colored) to branchpoint 1.180 (colored)
SVN rev 195197 on 2009-06-30 17:10:08Z by avg MFC 185295, 185341, 185343: cpu identification improvements Goal of this MFC is to minimize unnecessary code differences between head and the branch, and to improve/fix invariant TSC detection for a wide range of CPUs. 185295 by takawata: Honor AMDPM_TSC_INVARIANT for Intel CPUs (i386 only) 185341 by jkim: Introduce cpu_vendor_id... 185343 by jkim: Use newly introduced cpu_vendor_id... These revision are bundled together because all intermediate revisions have one or more of the following deficiencies: o AMDPM_TSC_INVARIANT bit (CPUID.0x80000007.EDX[8]) is not honored for Intel CPUs; o AMD-specific CPU model/revision checks are performed on Intel CPUs. Nod from: jkim
Revision 1.180.2.8 / (download) - annotate - [select for diffs], Tue Jun 30 14:11:43 2009 UTC (2 years, 7 months ago) by avg
Branch: RELENG_7
Changes since 1.180.2.7: +0 -298
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Diff to previous 1.180.2.7 (colored) to branchpoint 1.180 (colored)
SVN rev 195193 on 2009-06-30 14:11:43Z by avg MFC 179229 (alc), 195188: The VM system no longer uses setPQL2(). Remove it and its helpers. Drop unused extern declarations in amd64 that seem to have been related. Reviewed by: alc
Revision 1.180.2.7 / (download) - annotate - [select for diffs], Fri Jun 12 20:41:44 2009 UTC (2 years, 7 months ago) by jkim
Branch: RELENG_7
Changes since 1.180.2.6: +8 -8
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Diff to previous 1.180.2.6 (colored) to branchpoint 1.180 (colored)
SVN rev 194075 on 2009-06-12 20:41:44Z by jkim MFC: r175904, r175905, r186009 Sync amd64 and i386 CPUID feature flags with -CURRENT. - amd64 only: DTES64, SSE4.1, SSE4.2, x2APIC, POPCNT - both: ABM, SSE4A, MAS, OSVW, IBS, SSE5, SKINIT, WDT PR: kern/135202
Revision 1.202 / (download) - annotate - [select for diffs], Mon May 4 18:05:27 2009 UTC (2 years, 9 months ago) by jkim
Branch: MAIN
CVS Tags: RELENG_8_BP
Branch point for: RELENG_8
Changes since 1.201: +18 -11
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Diff to previous 1.201 (colored)
SVN rev 191788 on 2009-05-04 18:05:27Z by jkim Unlock the largest standard CPUID on Intel CPUs for both amd64 and i386 and fix SMP topology detection. On i386, we extend it to cover Core, Core 2, and Core i7 processors, not just Pentium 4 family, and move it to better place. On amd64, all supported Intel CPUs should have this MSR.
Revision 1.201 / (download) - annotate - [select for diffs], Wed Apr 29 06:54:40 2009 UTC (2 years, 9 months ago) by jeff
Branch: MAIN
Changes since 1.200: +0 -26
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Diff to previous 1.200 (colored)
SVN rev 191648 on 2009-04-29 06:54:40Z by jeff - Add support for cpuid leaf 0xb. This allows us to determine the topology of nehalem/corei7 based systems. - Remove the cpu_cores/cpu_logical detection from identcpu. - Describe the layout of the system in cpu_mp_announce(). Sponsored by: Nokia
Revision 1.180.2.6.2.1 / (download) - annotate - [select for diffs], Wed Apr 15 03:14:26 2009 UTC (2 years, 9 months ago) by kensmith
Branch: RELENG_7_2
CVS Tags: RELENG_7_2_0_RELEASE
Changes since 1.180.2.6: +0 -0
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Diff to previous 1.180.2.6 (colored) next main 1.180.2.7 (colored)
SVN rev 191087 on 2009-04-15 03:14:26Z by kensmith Create releng/7.2 from stable/7 in preparation for 7.2-RELEASE. Approved by: re (implicit)
Revision 1.200 / (download) - annotate - [select for diffs], Thu Jan 22 21:04:46 2009 UTC (3 years ago) by jkim
Branch: MAIN
Changes since 1.199: +2 -1
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Diff to previous 1.199 (colored)
SVN rev 187598 on 2009-01-22 21:04:46Z by jkim VIA Nano processor has a special MSR (CENT_HARDWARECTRL3) bit 32 to determine whether TSC is P-state invariant or not. In fact, this MSR is writable but we just leave it at the BIOS default for now.
Revision 1.180.2.6 / (download) - annotate - [select for diffs], Wed Jan 21 21:28:21 2009 UTC (3 years ago) by jkim
Branch: RELENG_7
CVS Tags: RELENG_7_2_BP
Branch point for: RELENG_7_2
Changes since 1.180.2.5: +9 -2
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Diff to previous 1.180.2.5 (colored) to branchpoint 1.180 (colored)
SVN rev 187572 on 2009-01-21 21:28:21Z by jkim MFC: Set tsc_is_invariant for some known AMD CPUs even if BIOS does not advertise it.
Revision 1.180.2.5 / (download) - annotate - [select for diffs], Wed Jan 21 20:53:36 2009 UTC (3 years ago) by jkim
Branch: RELENG_7
Changes since 1.180.2.4: +11 -2
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Diff to previous 1.180.2.4 (colored) to branchpoint 1.180 (colored)
SVN rev 187567 on 2009-01-21 20:53:36Z by jkim MFC: Turn off CPU frequency change notifiers when the TSC is P-state invariant or it is forced by setting 'kern.timecounter.invariant_tsc' tunable to non-zero.
Revision 1.180.2.4 / (download) - annotate - [select for diffs], Wed Jan 21 20:16:11 2009 UTC (3 years ago) by jkim
Branch: RELENG_7
Changes since 1.180.2.3: +4 -0
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Diff to previous 1.180.2.3 (colored) to branchpoint 1.180 (colored)
SVN rev 187565 on 2009-01-21 20:16:11Z by jkim MFC: Detect Advanced Power Management Information for AMD CPUs.
Revision 1.180.2.3 / (download) - annotate - [select for diffs], Sun Jan 18 12:16:45 2009 UTC (3 years ago) by stas
Branch: RELENG_7
Changes since 1.180.2.2: +2 -2
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Diff to previous 1.180.2.2 (colored) to branchpoint 1.180 (colored)
SVN rev 187390 on 2009-01-18 12:16:45Z by stas - Merge r183151: Recognize SAVE and OSXSAVE extended processor features.
Revision 1.199 / (download) - annotate - [select for diffs], Mon Jan 12 22:01:49 2009 UTC (3 years ago) by jkim
Branch: MAIN
Changes since 1.198: +12 -2
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Diff to previous 1.198 (colored)
SVN rev 187118 on 2009-01-12 22:01:49Z by jkim Add basic i386 support for VIA Nano processors.
Revision 1.198 / (download) - annotate - [select for diffs], Fri Dec 12 23:17:00 2008 UTC (3 years, 1 month ago) by jkim
Branch: MAIN
Changes since 1.197: +8 -8
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Diff to previous 1.197 (colored)
SVN rev 186009 on 2008-12-12 23:17:00Z by jkim Add more CPUID bits from AMD CPUID Specification Rev. 2.28.
Revision 1.197 / (download) - annotate - [select for diffs], Sun Nov 30 00:11:48 2008 UTC (3 years, 2 months ago) by mav
Branch: MAIN
Changes since 1.196: +5 -1
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Diff to previous 1.196 (colored)
SVN rev 185461 on 2008-11-30 00:11:48Z by mav According to "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2", CPUs with family 0x6 and model above or 0xE and CPUs with family 0xF and model above or 0x3 have invariant TSC.
Revision 1.196 / (download) - annotate - [select for diffs], Wed Nov 26 19:29:33 2008 UTC (3 years, 2 months ago) by jkim
Branch: MAIN
Changes since 1.195: +13 -8
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Diff to previous 1.195 (colored)
SVN rev 185343 on 2008-11-26 19:29:33Z by jkim Use newly introduced cpu_vendor_id to make invariant TSC detection more clearer and merge r185295 to amd64.
Revision 1.195 / (download) - annotate - [select for diffs], Wed Nov 26 19:25:13 2008 UTC (3 years, 2 months ago) by jkim
Branch: MAIN
Changes since 1.194: +70 -37
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Diff to previous 1.194 (colored)
SVN rev 185341 on 2008-11-26 19:25:13Z by jkim Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "..."). Reviewed by: jhb, peter (early amd64 version)
Revision 1.194 / (download) - annotate - [select for diffs], Tue Nov 25 13:35:06 2008 UTC (3 years, 2 months ago) by takawata
Branch: MAIN
Changes since 1.193: +2 -1
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Diff to previous 1.193 (colored)
SVN rev 185295 on 2008-11-25 13:35:06Z by takawata Core i7 supports invaliant TSC and the presense is presented on this CPUID information, according to recently updated AP485.
Revision 1.180.2.2.2.1 / (download) - annotate - [select for diffs], Tue Nov 25 02:59:29 2008 UTC (3 years, 2 months ago) by kensmith
Branch: RELENG_7_1
CVS Tags: RELENG_7_1_0_RELEASE
Changes since 1.180.2.2: +0 -0
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Diff to previous 1.180.2.2 (colored) next main 1.180.2.3 (colored)
SVN rev 185281 on 2008-11-25 02:59:29Z by kensmith Create releng/7.1 in preparation for moving into RC phase of 7.1 release cycle. Approved by: re (implicit)
Revision 1.193 / (download) - annotate - [select for diffs], Wed Oct 22 21:03:30 2008 UTC (3 years, 3 months ago) by jkim
Branch: MAIN
Changes since 1.192: +1 -1
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Diff to previous 1.192 (colored)
SVN rev 184181 on 2008-10-22 21:03:30Z by jkim Really fix i386 test this time. A whole stack of pointyhat to me, please.
Revision 1.192 / (download) - annotate - [select for diffs], Wed Oct 22 17:30:37 2008 UTC (3 years, 3 months ago) by jkim
Branch: MAIN
Changes since 1.191: +9 -4
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Diff to previous 1.191 (colored)
SVN rev 184169 on 2008-10-22 17:30:37Z by jkim Add AMD Family 0Fh, Model 6Bh, Stepping 2 to the list of invariant TSCs and fix i386 test.
Revision 1.191 / (download) - annotate - [select for diffs], Wed Oct 22 14:45:30 2008 UTC (3 years, 3 months ago) by ache
Branch: MAIN
Changes since 1.190: +3 -3
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Diff to previous 1.190 (colored)
SVN rev 184161 on 2008-10-22 14:45:30Z by ache Fix compiler error with missing/unneded ')'
Revision 1.190 / (download) - annotate - [select for diffs], Wed Oct 22 00:01:53 2008 UTC (3 years, 3 months ago) by jkim
Branch: MAIN
Changes since 1.189: +3 -1
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Diff to previous 1.189 (colored)
SVN rev 184146 on 2008-10-22 00:01:53Z by jkim Set kern.timecounter.invariant_tsc to 1 for AMD CPU family 10h and higher even if BIOS does not advertise it.
Revision 1.189 / (download) - annotate - [select for diffs], Tue Oct 21 00:38:00 2008 UTC (3 years, 3 months ago) by jkim
Branch: MAIN
Changes since 1.188: +11 -2
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Diff to previous 1.188 (colored)
SVN rev 184102 on 2008-10-21 00:38:00Z by jkim Turn off CPU frequency change notifiers when the TSC is P-state invariant or it is forced by setting 'kern.timecounter.invariant_tsc' tunable to non-zero.
Revision 1.188 / (download) - annotate - [select for diffs], Tue Oct 21 00:17:55 2008 UTC (3 years, 3 months ago) by jkim
Branch: MAIN
Changes since 1.187: +4 -0
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Diff to previous 1.187 (colored)
SVN rev 184101 on 2008-10-21 00:17:55Z by jkim Detect Advanced Power Management Information for AMD CPUs.
Revision 1.180.2.2 / (download) - annotate - [select for diffs], Fri Oct 17 19:52:35 2008 UTC (3 years, 3 months ago) by jhb
Branch: RELENG_7
CVS Tags: RELENG_7_1_BP
Branch point for: RELENG_7_1
Changes since 1.180.2.1: +6 -6
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Diff to previous 1.180.2.1 (colored) to branchpoint 1.180 (colored)
SVN rev 183984 on 2008-10-17 19:52:35Z by jhb MFC: More CPUID feature flags: SSE4, X2APIC, POPCNT, DTES64, and 1GB large pages. Approved by: re (kib)
Revision 1.145.2.7.2.1 / (download) - annotate - [select for diffs], Thu Oct 2 02:57:24 2008 UTC (3 years, 4 months ago) by kensmith
Branch: RELENG_6_4
CVS Tags: RELENG_6_4_0_RELEASE
Changes since 1.145.2.7: +0 -0
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Diff to previous 1.145.2.7 (colored) next main 1.145.2.8 (colored)
SVN rev 183531 on 2008-10-02 02:57:24Z by kensmith Create releng/6.4 from stable/6 in preparation for 6.4-RC1. Approved by: re (implicit)
Revision 1.187 / (download) - annotate - [select for diffs], Thu Sep 18 18:51:32 2008 UTC (3 years, 4 months ago) by stas
Branch: MAIN
Changes since 1.186: +2 -2
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Diff to previous 1.186 (colored)
SVN rev 183151 on 2008-09-18 18:51:32Z by stas - Recognize SAVE and OSXSAVE extended processor features. Approved by: kib (mentor) MFC after: 1 month
Revision 1.186 / (download) - annotate - [select for diffs], Wed Sep 17 20:45:18 2008 UTC (3 years, 4 months ago) by jhb
Branch: MAIN
Changes since 1.185: +6 -6
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Diff to previous 1.185 (colored)
SVN rev 183128 on 2008-09-17 20:45:18Z by jhb MFamd64: More CPUID feature flags: SSE4, X2APIC, POPCNT, DTES64, and 1GB large pages. MFC after: 1 month
Revision 1.185 / (download) - annotate - [select for diffs], Fri May 23 04:03:53 2008 UTC (3 years, 8 months ago) by alc
Branch: MAIN
Changes since 1.184: +0 -298
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Diff to previous 1.184 (colored)
The VM system no longer uses setPQL2(). Remove it and its helpers.
Revision 1.145.2.7 / (download) - annotate - [select for diffs], Fri Mar 7 20:19:33 2008 UTC (3 years, 11 months ago) by jhb
Branch: RELENG_6
CVS Tags: RELENG_6_4_BP
Branch point for: RELENG_6_4
Changes since 1.145.2.6: +41 -26
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Diff to previous 1.145.2.6 (colored) to branchpoint 1.145 (colored)
MFC: VIA Padlock changes: - Read the brand string from VIA/IDT CPUs. - Add a VIA Padlock feature line in dmesg. - Support the newer Via C7 core (0x6d0).
Revision 1.180.2.1 / (download) - annotate - [select for diffs], Fri Mar 7 20:19:24 2008 UTC (3 years, 11 months ago) by jhb
Branch: RELENG_7
Changes since 1.180: +43 -23
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Diff to previous 1.180 (colored)
MFC: VIA Padlock changes: - Read the brand string from VIA/IDT CPUs. - Add a VIA Padlock feature line in dmesg. - Support the newer Via C7 core (0x6d0).
Revision 1.184 / (download) - annotate - [select for diffs], Sun Mar 2 07:58:40 2008 UTC (3 years, 11 months ago) by jeff
Branch: MAIN
Changes since 1.183: +6 -1
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Diff to previous 1.183 (colored)
- Remove the old smp cpu topology specification with a new, more flexible tree structure that encodes the level of cache sharing and other properties. - Provide several convenience functions for creating one and two level cpu trees as well as a default flat topology. The system now always has some topology. - On i386 and amd64 create a seperate level in the hierarchy for HTT and multi-core cpus. This will allow the scheduler to intelligently load balance non-uniform cores. Presently we don't detect what level of the cache hierarchy is shared at each level in the topology. - Add a mechanism for testing common topologies that have more information than the MD code is able to provide via the kern.smp.topology tunable. This should be considered a debugging tool only and not a stable api. Sponsored by: Nokia
Revision 1.183 / (download) - annotate - [select for diffs], Fri Feb 29 19:18:09 2008 UTC (3 years, 11 months ago) by jhb
Branch: MAIN
Changes since 1.182: +41 -24
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Diff to previous 1.182 (colored)
With the recent change to enable CPU brands from the VIA chips, the code to add padlock features to the CPU model on VIA CPUs was no longer effective. Change the code to instead output a separate printf during dmesg for VIA Padlock features similar to other cpuid feature bitmasks. MFC after: 1 week
Revision 1.182 / (download) - annotate - [select for diffs], Thu Feb 28 17:59:54 2008 UTC (3 years, 11 months ago) by jhb
Branch: MAIN
Changes since 1.181: +2 -2
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Diff to previous 1.181 (colored)
- Check for the extended CPUID registers on VIA CPUs so we can get the brand string. - Fix a nit in the previous commit. "Eden" is a product name, not a core name. The new ID is still for an "Esther" core.
Revision 1.181 / (download) - annotate - [select for diffs], Mon Feb 25 22:42:33 2008 UTC (3 years, 11 months ago) by jhb
Branch: MAIN
Changes since 1.180: +3 -0
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Diff to previous 1.180 (colored)
Support the VIA C7 Eden CPU and treat it just like a C7 Esther. We may want to adjust this code to just assume that all CPUs >= Esther should be checked for the extended cpuid flags register. MFC after: 3 days PR: i386/119491
Revision 1.145.2.6 / (download) - annotate - [select for diffs], Fri Sep 28 08:26:16 2007 UTC (4 years, 4 months ago) by des
Branch: RELENG_6
CVS Tags: RELENG_6_3_BP,
RELENG_6_3_0_RELEASE,
RELENG_6_3
Changes since 1.145.2.5: +12 -17
lines
Diff to previous 1.145.2.5 (colored) to branchpoint 1.145 (colored)
MFC: remove confusing boot message, add feature bits
Revision 1.180 / (download) - annotate - [select for diffs], Tue May 29 19:39:18 2007 UTC (4 years, 8 months ago) by des
Branch: MAIN
CVS Tags: RELENG_7_BP,
RELENG_7_0_BP,
RELENG_7_0_0_RELEASE,
RELENG_7_0
Branch point for: RELENG_7
Changes since 1.179: +1 -1
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Diff to previous 1.179 (colored)
Add descriptive comment to PDCM entry.
Revision 1.179 / (download) - annotate - [select for diffs], Tue May 29 19:25:50 2007 UTC (4 years, 8 months ago) by des
Branch: MAIN
Changes since 1.178: +1 -6
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Diff to previous 1.178 (colored)
Remove a pointless bootverbose message. MFC after: 3 days
Revision 1.178 / (download) - annotate - [select for diffs], Tue May 29 19:21:53 2007 UTC (4 years, 8 months ago) by des
Branch: MAIN
Changes since 1.177: +1 -1
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Diff to previous 1.177 (colored)
Add feature name for features2 bit 15. PR: i386/113133 Submitted by: Pankov Pavel <pankov_p@mail.ru> MFC after: 3 days
Revision 1.177 / (download) - annotate - [select for diffs], Wed Apr 18 10:08:24 2007 UTC (4 years, 9 months ago) by phk
Branch: MAIN
Changes since 1.176: +8 -0
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Diff to previous 1.176 (colored)
On AMD's Geode LX: Force the TSC to run through core-suspension so we can use it as a timecounter. Sponsored by: Soekris Engineering
Revision 1.176 / (download) - annotate - [select for diffs], Fri Apr 6 18:15:02 2007 UTC (4 years, 10 months ago) by ru
Branch: MAIN
Changes since 1.175: +14 -15
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Diff to previous 1.175 (colored)
Add the PG_NX support for i386/PAE. Reviewed by: alc
Revision 1.175 / (download) - annotate - [select for diffs], Mon Mar 26 18:03:29 2007 UTC (4 years, 10 months ago) by njl
Branch: MAIN
Changes since 1.174: +17 -0
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Diff to previous 1.174 (colored)
Add an interface for drivers to be notified of changes to CPU frequency. cpufreq_pre_change is called before the change, giving each driver a chance to revoke the change. cpufreq_post_change provides the results of the change (success or failure). cpufreq_levels_changed gives the unit number of the cpufreq device whose number of available levels has changed. Hook in all the drivers I could find that needed it. * TSC: update TSC frequency value. When the available levels change, take the highest possible level and notify the timecounter set_cputicker() of that freq. This gets rid of the "calcru: runtime went backwards" messages. * identcpu: updates the sysctl hw.clockrate value * Profiling: if profiling is active when the clock changes, let the user know the results may be inaccurate. Reviewed by: bde, phk MFC after: 1 month
Revision 1.174 / (download) - annotate - [select for diffs], Tue Mar 20 20:22:45 2007 UTC (4 years, 10 months ago) by jkim
Branch: MAIN
Changes since 1.173: +2 -2
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Diff to previous 1.173 (colored)
- Add macros for newly added CPUID bits in the corresponding header files. - Use correct capticalization in xTPR as Intel uses in their documents. - Use proper description instead of vendor code name in comment.
Revision 1.173 / (download) - annotate - [select for diffs], Mon Mar 19 05:23:42 2007 UTC (4 years, 10 months ago) by sam
Branch: MAIN
Changes since 1.172: +2 -2
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Diff to previous 1.172 (colored)
display two new Intel feature bits Submitted by: "Rui Paulo" <rpaulo@gmail.com> MFC after: 2 weeks
Revision 1.172 / (download) - annotate - [select for diffs], Mon Mar 12 20:27:21 2007 UTC (4 years, 11 months ago) by jkim
Branch: MAIN
Changes since 1.171: +1 -1
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Diff to previous 1.171 (colored)
Add another CPUID for AMD CPUs and fix style(9) while I am here.
Revision 1.171 / (download) - annotate - [select for diffs], Tue Jan 9 19:23:21 2007 UTC (5 years, 1 month ago) by jkim
Branch: MAIN
Changes since 1.170: +2 -2
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Diff to previous 1.170 (colored)
Add SSSE3 extensions and correct CNXT-ID spelling for Intel processors.
Revision 1.170 / (download) - annotate - [select for diffs], Tue Nov 7 18:48:18 2006 UTC (5 years, 3 months ago) by jhb
Branch: MAIN
Changes since 1.169: +0 -8
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Diff to previous 1.169 (colored)
Remove old XXX comment about possibly adding a print_Intel_info() function to dump CPUID level=2 stuff. A print_INTEL_info() function that does just that was added a while ago.
Revision 1.145.2.5 / (download) - annotate - [select for diffs], Tue Aug 8 08:41:34 2006 UTC (5 years, 6 months ago) by mr
Branch: RELENG_6
CVS Tags: RELENG_6_2_BP,
RELENG_6_2_0_RELEASE,
RELENG_6_2
Changes since 1.145.2.4: +2 -1
lines
Diff to previous 1.145.2.4 (colored) to branchpoint 1.145 (colored)
MFC: Dont overwrite cpu_model in the case of Via's C3-CPU.
Revision 1.169 / (download) - annotate - [select for diffs], Fri Aug 4 13:49:16 2006 UTC (5 years, 6 months ago) by mr
Branch: MAIN
Changes since 1.168: +2 -1
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Diff to previous 1.168 (colored)
Dont overwrite cpu_model in the case of Via's C3-CPU. Noticed by: Mike Tancsa MFC after: 2 days
Revision 1.168 / (download) - annotate - [select for diffs], Tue Aug 1 01:23:39 2006 UTC (5 years, 6 months ago) by obrien
Branch: MAIN
Changes since 1.167: +2 -2
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Diff to previous 1.167 (colored)
Correct spelling of 3DNow!.
Revision 1.145.2.4 / (download) - annotate - [select for diffs], Fri Jul 21 15:12:02 2006 UTC (5 years, 6 months ago) by mr
Branch: RELENG_6
Changes since 1.145.2.3: +24 -8
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Diff to previous 1.145.2.3 (colored) to branchpoint 1.145 (colored)
MFC VIA C7 support. Obtained from: mostly OpenBSD
Revision 1.167 / (download) - annotate - [select for diffs], Wed Jul 12 16:52:55 2006 UTC (5 years, 7 months ago) by mr
Branch: MAIN
Changes since 1.166: +1 -1
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Diff to previous 1.166 (colored)
fix typo in identcpu.c and add one define to specialreg.h. MFC after: 1 week
Revision 1.166 / (download) - annotate - [select for diffs], Wed Jul 12 14:59:06 2006 UTC (5 years, 7 months ago) by mr
Branch: MAIN
Changes since 1.165: +0 -0
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Diff to previous 1.165 (colored)
forgot to add MFC, since its used on -stable and compile-tested on -current. MFC after: 1 week
Revision 1.165 / (download) - annotate - [select for diffs], Wed Jul 12 14:52:32 2006 UTC (5 years, 7 months ago) by mr
Branch: MAIN
Changes since 1.164: +20 -8
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Diff to previous 1.164 (colored)
First step to identify and initialize the newer VIA C7 CPU as found in a VIA EPIA EN-15000 board. Obtained from: large parts from OpenBSD
Revision 1.164 / (download) - annotate - [select for diffs], Wed Jul 12 06:04:12 2006 UTC (5 years, 7 months ago) by jkim
Branch: MAIN
Changes since 1.163: +2 -2
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Diff to previous 1.163 (colored)
Add two new CPUID bits for AMD CPUs, i. e., SVM and extended APIC register.
Revision 1.163 / (download) - annotate - [select for diffs], Mon Jun 19 07:51:47 2006 UTC (5 years, 7 months ago) by davidxu
Branch: MAIN
Changes since 1.162: +11 -0
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Diff to previous 1.162 (colored)
Clear bit 22 in MSR IA32_MISC_ENABLE, according to Intel document, when the bit 22 is set to 1, CPUID with EAX=0 returns a maximum value in EAX[7..0] of 3, when set to 0(default), CPUID with EAX=0 returns the number corresponding to the maximum standard function supported. On my machine, BIOS sets the bit to 1 to make it to be compatible with old OS, this causes dual-core Pentium-D (two physical cores) to be identified as hyperthreading (two logical cores) by function mp_topology().
Revision 1.162 / (download) - annotate - [select for diffs], Mon Apr 24 22:56:57 2006 UTC (5 years, 9 months ago) by jkim
Branch: MAIN
Changes since 1.161: +1 -1
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Diff to previous 1.161 (colored)
Add another Intel CPU feature flag, xTPR (Send Task Priority Messages).
Revision 1.161 / (download) - annotate - [select for diffs], Mon Apr 24 22:23:52 2006 UTC (5 years, 9 months ago) by jkim
Branch: MAIN
Changes since 1.160: +2 -1
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Diff to previous 1.160 (colored)
Check if deterministic cache parameters leaf is valid before use.
Revision 1.145.2.2.2.1 / (download) - annotate - [select for diffs], Mon Apr 24 18:24:30 2006 UTC (5 years, 9 months ago) by jkim
Branch: RELENG_6_1
CVS Tags: RELENG_6_1_0_RELEASE
Changes since 1.145.2.2: +81 -14
lines
Diff to previous 1.145.2.2 (colored) next main 1.145.2.3 (colored)
MFC: Multicore detection. - Print number of physical/logical cores and more CPUID info. - Add newer CPUID definitions for future use. - Correct few MSR addresses while I am here. - Fix spelling mistake. Approved by: re (hrs)
Revision 1.145.2.3 / (download) - annotate - [select for diffs], Mon Apr 24 18:21:55 2006 UTC (5 years, 9 months ago) by jkim
Branch: RELENG_6
Changes since 1.145.2.2: +81 -14
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Diff to previous 1.145.2.2 (colored) to branchpoint 1.145 (colored)
MFC: Multicore detection. - Print number of physical/logical cores and more CPUID info. - Add newer CPUID definitions for future use. - Correct few MSR addresses while I am here. - Fix spelling mistake. Approved by: re (hrs)
Revision 1.160 / (download) - annotate - [select for diffs], Fri Mar 3 18:54:05 2006 UTC (5 years, 11 months ago) by netchild
Branch: MAIN
Changes since 1.159: +133 -78
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Diff to previous 1.159 (colored)
- use a more common style to print memory sizes - add some more cache sizes (2nd and 3rd level) [1] Submitted by: HATANOU Tomomi <hatanou@infolab.ne.jp> [1] PR: 91328 [1]
Revision 1.145.2.2 / (download) - annotate - [select for diffs], Thu Feb 23 15:03:42 2006 UTC (5 years, 11 months ago) by dwmalone
Branch: RELENG_6
CVS Tags: RELENG_6_1_BP
Branch point for: RELENG_6_1
Changes since 1.145.2.1: +2 -2
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Diff to previous 1.145.2.1 (colored) to branchpoint 1.145 (colored)
MFC: Print Virtual Machine Extensions feature and remove stale comment. Approved by: re (scottl)
Revision 1.159 / (download) - annotate - [select for diffs], Wed Feb 15 14:48:59 2006 UTC (5 years, 11 months ago) by dwmalone
Branch: MAIN
Changes since 1.158: +2 -2
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Diff to previous 1.158 (colored)
It seems bit 5 of cpu_feature2 is the VMX (Virtual Machine Extensions) bit. While I'm here, delete a comment that was cut and past from the cpu_features code that doesn't belong here.
Revision 1.158 / (download) - annotate - [select for diffs], Thu Feb 9 09:10:54 2006 UTC (6 years ago) by yar
Branch: MAIN
Changes since 1.157: +24 -49
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Diff to previous 1.157 (colored)
Avoid calling CPUID function 0x02 if the CPU reports no support for it. The former code used to hang older Intel CPUs by trying to get non-existent TLB info 2^32 times. Reduce code duplication around the calls to CPUID 0x02 by using do-while loops. PR: i386/92977 Tested by: cy
Revision 1.157 / (download) - annotate - [select for diffs], Thu Feb 2 12:44:09 2006 UTC (6 years ago) by davidxu
Branch: MAIN
Changes since 1.156: +7 -1
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Diff to previous 1.156 (colored)
Under verbose mode, correctly report L2 cache information for CPU which supports CPUID function 8000_0006h. Tested on: Pentum-M 750
Revision 1.156 / (download) - annotate - [select for diffs], Thu Feb 2 11:54:40 2006 UTC (6 years ago) by davidxu
Branch: MAIN
Changes since 1.155: +8 -3
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Diff to previous 1.155 (colored)
Fix bug in L2 cache size detection code for CPU which supports CPUID function 8000_0006h. Tested on: Pentum-M 750
Revision 1.155 / (download) - annotate - [select for diffs], Thu Feb 2 06:35:50 2006 UTC (6 years ago) by davidxu
Branch: MAIN
Changes since 1.154: +2 -2
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Diff to previous 1.154 (colored)
Correctly report L2 cache size according to its code comment. Tested on my Dual PIII machine.
Revision 1.154 / (download) - annotate - [select for diffs], Wed Jan 4 20:11:04 2006 UTC (6 years, 1 month ago) by netchild
Branch: MAIN
Changes since 1.153: +0 -16
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Diff to previous 1.153 (colored)
We don't support I386_CPU in 6.0 and later. This file can be cleaned up some to assume that '#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)' is true. Suggested by: jhb Reviewed by: jhb
Revision 1.153 / (download) - annotate - [select for diffs], Wed Jan 4 12:57:02 2006 UTC (6 years, 1 month ago) by netchild
Branch: MAIN
Changes since 1.152: +39 -19
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Diff to previous 1.152 (colored)
- Make sure the cpu_exthigh variable is initialized (page coloring case). [1] - Remove a conditional in the AMD cache detection, it's always false. [2] - Don't try to detect a cache if only compiled for i386. Analyzed by: Antoine Brodin <antoine.brodin@laposte.net> [1] Submitted by: Antoine Brodin <antoine.brodin@laposte.net> [2]
Revision 1.152 / (download) - annotate - [select for diffs], Sat Dec 31 14:39:17 2005 UTC (6 years, 1 month ago) by netchild
Branch: MAIN
Changes since 1.151: +466 -0
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Diff to previous 1.151 (colored)
MI changes: - provide an interface (macros) to the page coloring part of the VM system, this allows to try different coloring algorithms without the need to touch every file [1] - make the page queue tuning values readable: sysctl vm.stats.pagequeue - autotuning of the page coloring values based upon the cache size instead of options in the kernel config (disabling of the page coloring as a kernel option is still possible) MD changes: - detection of the cache size: only IA32 and AMD64 (untested) contains cache size detection code, every other arch just comes with a dummy function (this results in the use of default values like it was the case without the autotuning of the page coloring) - print some more info on Intel CPU's (like we do on AMD and Transmeta CPU's) Note to AMD owners (IA32 and AMD64): please run "sysctl vm.stats.pagequeue" and report if the cache* values are zero (= bug in the cache detection code) or not. Based upon work by: Chad David <davidc@acns.ab.ca> [1] Reviewed by: alc, arch (in 2004) Discussed with: alc, Chad David, arch (in 2004)
Revision 1.151 / (download) - annotate - [select for diffs], Mon Dec 5 14:22:11 2005 UTC (6 years, 2 months ago) by ru
Branch: MAIN
Changes since 1.150: +1 -1
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Diff to previous 1.150 (colored)
Prepare for MACHINE and hw.machine switching to "pc98" on FreeBSD/pc98. Reviewed by: nyan
Revision 1.150 / (download) - annotate - [select for diffs], Thu Nov 17 02:32:39 2005 UTC (6 years, 2 months ago) by obrien
Branch: MAIN
Changes since 1.149: +1 -1
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Diff to previous 1.149 (colored)
Fix spelling mistake. Submitted by: kris
Revision 1.145.2.1 / (download) - annotate - [select for diffs], Mon Nov 7 08:41:12 2005 UTC (6 years, 3 months ago) by obrien
Branch: RELENG_6
Changes since 1.145: +9 -0
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Diff to previous 1.145 (colored)
MFC: for AMD dual-core processors, nullify CPUID.HTT.
Revision 1.149 / (download) - annotate - [select for diffs], Mon Oct 17 23:23:20 2005 UTC (6 years, 3 months ago) by jkim
Branch: MAIN
Changes since 1.148: +4 -3
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Diff to previous 1.148 (colored)
Redo physical/logical CPU count. Suggested by: jhb
Revision 1.148 / (download) - annotate - [select for diffs], Mon Oct 17 15:51:28 2005 UTC (6 years, 3 months ago) by jkim
Branch: MAIN
Changes since 1.147: +3 -2
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Diff to previous 1.147 (colored)
Split displaying number of physical and logical cores.
Revision 1.147 / (download) - annotate - [select for diffs], Sun Oct 16 08:58:27 2005 UTC (6 years, 3 months ago) by obrien
Branch: MAIN
Changes since 1.146: +9 -0
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Diff to previous 1.146 (colored)
For AMD processors, nullify CPUID.HTT. FreeBSD has no need for the information it conveys, and it is only confusing people. This fixes incorrect output in the previous commit.
Revision 1.146 / (download) - annotate - [select for diffs], Fri Oct 14 22:52:00 2005 UTC (6 years, 3 months ago) by jkim
Branch: MAIN
Changes since 1.145: +78 -13
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Diff to previous 1.145 (colored)
- Print number of physical/logical cores and more CPUID info. - Add newer CPUID definitions for future use. Many thanks to Mike Tancsa <mike at sentex dot net> for providing test cases for Intel Pentium D and AMD Athlon 64 X2. Approved by: anholt (mentor)
Revision 1.145 / (download) - annotate - [select for diffs], Thu Jun 30 06:44:34 2005 UTC (6 years, 7 months ago) by peter
Branch: MAIN
CVS Tags: RELENG_6_BP,
RELENG_6_0_BP,
RELENG_6_0_0_RELEASE,
RELENG_6_0
Branch point for: RELENG_6
Changes since 1.144: +82 -91
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Diff to previous 1.144 (colored)
Begin promoting the AMD-originated feature flags to first class flags, now that newer Intel cpu hardware implements them too. This includes things like the NX (pte no-execute) flag for execute protection. We'll need to reference this for implementing no-exec in pmap.c at some point. Some feature flags are duplicated in both the Intel-orignated bits and the AMD bits. Suppress the the duplicates correctly - the old code assumed they were a 1:1 mapping which is not correct. We can't just mask off the bits present in cpu_feature. Converge with amd64 where this originated from. Intel cpu's that implement any AMD features will report them in dmesg now. Approved by: re
Revision 1.144 / (download) - annotate - [select for diffs], Sun May 29 17:43:24 2005 UTC (6 years, 8 months ago) by schweikh
Branch: MAIN
Changes since 1.143: +1 -1
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Diff to previous 1.143 (colored)
Chop a '>' in a feature name (RSVD2>) that snuck in; this now balances the <> flags displayed at boot, e.g. without this Features2=0x41d<SSE3,RSVD2>,MON,DS_CPL,CNTX-ID> MFC after: 1 week
Revision 1.143 / (download) - annotate - [select for diffs], Mon May 16 09:47:53 2005 UTC (6 years, 8 months ago) by obrien
Branch: MAIN
Changes since 1.142: +37 -0
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Diff to previous 1.142 (colored)
Add the 2nd word of IA32 feature flags. This includes things such as SSE3. Obtained from: sys/amd64/amd64/identcpu.
Revision 1.142 / (download) - annotate - [select for diffs], Wed Mar 2 21:33:25 2005 UTC (6 years, 11 months ago) by joerg
Branch: MAIN
Changes since 1.141: +2 -2
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Diff to previous 1.141 (colored)
netchild's mega-patch to isolate compiler dependencies into a central place. This moves the dependency on GCC's and other compiler's features into the central sys/cdefs.h file, while the individual source files can then refer to #ifdef __COMPILER_FEATURE_FOO where they by now used to refer to #if __GNUC__ > 3.1415 && __BARC__ <= 42. By now, GCC and ICC (the Intel compiler) have been actively tested on IA32 platforms by netchild. Extension to other compilers is supposed to be possible, of course. Submitted by: netchild Reviewed by: various developers on arch@, some time ago
Revision 1.141 / (download) - annotate - [select for diffs], Sun Dec 12 05:53:57 2004 UTC (7 years, 2 months ago) by njl
Branch: MAIN
Changes since 1.140: +0 -2
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Diff to previous 1.140 (colored)
Move the author's copyright notice to match the initial LongRun import now that we have split out this support into longrun.c
Revision 1.140 / (download) - annotate - [select for diffs], Tue Nov 16 20:42:31 2004 UTC (7 years, 2 months ago) by jhb
Branch: MAIN
Changes since 1.139: +1 -8
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Diff to previous 1.139 (colored)
Initiate deorbit burn sequence for 80386 support in FreeBSD: Remove 80386 (I386_CPU) support from the kernel.
Revision 1.139 / (download) - annotate - [select for diffs], Thu Jun 3 21:14:53 2004 UTC (7 years, 8 months ago) by phk
Branch: MAIN
CVS Tags: RELENG_5_BP,
RELENG_5_5_BP,
RELENG_5_5_0_RELEASE,
RELENG_5_5,
RELENG_5_4_BP,
RELENG_5_4_0_RELEASE,
RELENG_5_4,
RELENG_5_3_BP,
RELENG_5_3_0_RELEASE,
RELENG_5_3,
RELENG_5
Changes since 1.138: +2 -0
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Diff to previous 1.138 (colored)
The NatSemi (now AMD) Geode SC1100 needs special treatment here and there because it is an embedded gadget. Give it it's own value for the "cpu" variable and add code to reset it lacking a keyboard controller.
Revision 1.138 / (download) - annotate - [select for diffs], Sun May 30 15:16:07 2004 UTC (7 years, 8 months ago) by phk
Branch: MAIN
Changes since 1.137: +4 -1
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Diff to previous 1.137 (colored)
struct cpu_nameclass is a private to identcpu.c, move it there.
Revision 1.137 / (download) - annotate - [select for diffs], Fri Apr 9 17:00:03 2004 UTC (7 years, 10 months ago) by markm
Branch: MAIN
Changes since 1.136: +1 -1
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Diff to previous 1.136 (colored)
I hate noticing bugs after committing. :-( ALWAYS set up the CPU base identity string. THEN optionally add features.
Revision 1.136 / (download) - annotate - [select for diffs], Fri Apr 9 15:01:44 2004 UTC (7 years, 10 months ago) by markm
Branch: MAIN
Changes since 1.135: +11 -1
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Diff to previous 1.135 (colored)
Add extra output to show when VIA C3 Nehemiah CPUs have hardware Random Number Generator (RNG) and/or Advanced Cryptography Engine (ACE).
Revision 1.80.2.17 / (download) - annotate - [select for diffs], Tue Apr 6 01:40:30 2004 UTC (7 years, 10 months ago) by imp
Branch: RELENG_4
CVS Tags: RELENG_4_11_BP,
RELENG_4_11_0_RELEASE,
RELENG_4_11,
RELENG_4_10_BP,
RELENG_4_10_0_RELEASE,
RELENG_4_10
Changes since 1.80.2.16: +13 -1
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Diff to previous 1.80.2.16 (colored) to branchpoint 1.80 (colored) next main 1.81 (colored)
MFC 1.128: Improve identification of VIA C3 Samuel, Samuel2, Ezra, Ezra-T and Nehemiah CPUs. MFC Forgotten by: imp MFC Reminder: Yasuhiro KIMURA-san.
Revision 1.135 / (download) - annotate - [select for diffs], Mon Apr 5 10:12:19 2004 UTC (7 years, 10 months ago) by dfr
Branch: MAIN
Changes since 1.134: +2 -0
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Diff to previous 1.134 (colored)
Print cpu features for crusoe processors.
Revision 1.134 / (download) - annotate - [select for diffs], Fri Mar 12 21:45:29 2004 UTC (7 years, 11 months ago) by trhodes
Branch: MAIN
Changes since 1.133: +2 -2
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Diff to previous 1.133 (colored)
These are changes to allow to use the Intel C/C++ compiler (lang/icc)
to build the kernel. It doesn't affect the operation if gcc.
Most of the changes are just adding __INTEL_COMPILER to #ifdef's, as
icc v8 may define __GNUC__ some parts may look strange but are
necessary.
Additional changes:
- in_cksum.[ch]:
* use a generic C version instead of the assembly version in the !gcc
case (ASM code breaks with the optimizations icc does)
-> no bad checksums with an icc compiled kernel
Help from: andre, grehan, das
Stolen from: alpha version via ppc version
The entire checksum code should IMHO be replaced with the DragonFly
version (because it isn't guaranteed future revisions of gcc will
include similar optimizations) as in:
---snip---
Revision Changes Path
1.12 +1 -0 src/sys/conf/files.i386
1.4 +142 -558 src/sys/i386/i386/in_cksum.c
1.5 +33 -69 src/sys/i386/include/in_cksum.h
1.5 +2 -0 src/sys/netinet/igmp.c
1.6 +0 -1 src/sys/netinet/in.h
1.6 +2 -0 src/sys/netinet/ip_icmp.c
1.4 +3 -4 src/contrib/ipfilter/ip_compat.h
1.3 +1 -2 src/sbin/natd/icmp.c
1.4 +0 -1 src/sbin/natd/natd.c
1.48 +1 -0 src/sys/conf/files
1.2 +0 -1 src/sys/conf/files.amd64
1.13 +0 -1 src/sys/conf/files.i386
1.5 +0 -1 src/sys/conf/files.pc98
1.7 +1 -1 src/sys/contrib/ipfilter/netinet/fil.c
1.10 +2 -3 src/sys/contrib/ipfilter/netinet/ip_compat.h
1.10 +1 -1 src/sys/contrib/ipfilter/netinet/ip_fil.c
1.7 +1 -1 src/sys/dev/netif/txp/if_txp.c
1.7 +1 -1 src/sys/net/ip_mroute/ip_mroute.c
1.7 +1 -2 src/sys/net/ipfw/ip_fw2.c
1.6 +1 -2 src/sys/netinet/igmp.c
1.4 +158 -116 src/sys/netinet/in_cksum.c
1.6 +1 -1 src/sys/netinet/ip_gre.c
1.7 +1 -2 src/sys/netinet/ip_icmp.c
1.10 +1 -1 src/sys/netinet/ip_input.c
1.10 +1 -2 src/sys/netinet/ip_output.c
1.13 +1 -2 src/sys/netinet/tcp_input.c
1.9 +1 -2 src/sys/netinet/tcp_output.c
1.10 +1 -1 src/sys/netinet/tcp_subr.c
1.10 +1 -1 src/sys/netinet/tcp_syncache.c
1.9 +1 -2 src/sys/netinet/udp_usrreq.c
1.5 +1 -2 src/sys/netinet6/ipsec.c
1.5 +1 -2 src/sys/netproto/ipsec/ipsec.c
1.5 +1 -1 src/sys/netproto/ipsec/ipsec_input.c
1.4 +1 -2 src/sys/netproto/ipsec/ipsec_output.c
and finally remove
sys/i386/i386 in_cksum.c
sys/i386/include in_cksum.h
---snip---
- endian.h:
* DTRT in C++ mode
- quad.h:
* we don't use gcc v1 anymore, remove support for it
Suggested by: bde (long ago)
- assym.h:
* avoid zero-length arrays (remove dependency on a gcc specific
feature)
This change changes the contents of the object file, but as it's
only used to generate some values for a header, and the generator
knows how to handle this, there's no impact in the gcc case.
Explained by: bde
Submitted by: Marius Strobl <marius@alchemy.franken.de>
- aicasm.c:
* minor change to teach it about the way icc spells "-nostdinc"
Not approved by: gibbs (no reply to my mail)
- bump __FreeBSD_version (lang/icc needs to know about the changes)
Incarnations of this patch survive gcc compiles since a loooong time,
I use it on my desktop. An icc compiled kernel works since Nov. 2003
(exceptions: snd_* if used as modules), it survives a build of the
entire ports collection with icc.
Parts of this commit contains suggestions or submissions from
Marius Strobl <marius@alchemy.franken.de>.
Reviewed by: -arch
Submitted by: netchild
Revision 1.133 / (download) - annotate - [select for diffs], Sun Jan 25 09:59:16 2004 UTC (8 years ago) by sobomax
Branch: MAIN
Changes since 1.132: +0 -263
lines
Diff to previous 1.132 (colored)
Move LongRun support out of identcpu.c, where it hardly belongs, into its own file and make it opt-in, not mandatory, depending on CPU_ENABLE_LONGRUN config(8) option. Discussed with: nate MFC after: 2 weeks
Revision 1.132 / (download) - annotate - [select for diffs], Mon Nov 3 22:38:00 2003 UTC (8 years, 3 months ago) by jhb
Branch: MAIN
CVS Tags: RELENG_5_2_BP,
RELENG_5_2_1_RELEASE,
RELENG_5_2_0_RELEASE,
RELENG_5_2
Changes since 1.131: +2 -4
lines
Diff to previous 1.131 (colored)
Update includes for new interrupt code.
Revision 1.131 / (download) - annotate - [select for diffs], Mon Nov 3 14:59:05 2003 UTC (8 years, 3 months ago) by obrien
Branch: MAIN
Changes since 1.130: +3 -3
lines
Diff to previous 1.130 (colored)
Add AMD Features NX and LM.
Revision 1.130 / (download) - annotate - [select for diffs], Wed Sep 10 01:07:03 2003 UTC (8 years, 5 months ago) by jhb
Branch: MAIN
Changes since 1.129: +4 -2
lines
Diff to previous 1.129 (colored)
Add constants for entries in the IDT and use those instead of magic numbers.
Revision 1.129 / (download) - annotate - [select for diffs], Mon Aug 25 09:48:47 2003 UTC (8 years, 5 months ago) by obrien
Branch: MAIN
Changes since 1.128: +1 -1
lines
Diff to previous 1.128 (colored)
Fix copyright comment & FBSDID style nits. Requested by: bde
Revision 1.128 / (download) - annotate - [select for diffs], Fri Aug 15 06:02:24 2003 UTC (8 years, 5 months ago) by imp
Branch: MAIN
Changes since 1.127: +6 -12
lines
Diff to previous 1.127 (colored)
Improve the C3 CPU identification. I didn't notice that the CPU id was masked. However KIMURA Yasuhiro-san noticed my mistake and was kind enough to provide a better patch in PR 55581. I've merged that into the routine. Hopefully I've not overlooked anything this time. MFC After: 5 days
Revision 1.127 / (download) - annotate - [select for diffs], Thu Aug 14 15:17:49 2003 UTC (8 years, 6 months ago) by imp
Branch: MAIN
Changes since 1.126: +18 -0
lines
Diff to previous 1.126 (colored)
Add many new VIA C3 CPU types now that they appear to be available in machines (at least in Japan). Submitted by: Masahiko KIMOTO-san PR: 55578
Revision 1.126 / (download) - annotate - [select for diffs], Wed Aug 6 15:03:47 2003 UTC (8 years, 6 months ago) by phk
Branch: MAIN
Changes since 1.125: +12 -1
lines
Diff to previous 1.125 (colored)
Update to recognize Geode and note that the TSC seems broken.
Revision 1.57.2.17 / (download) - annotate - [select for diffs], Tue Aug 5 07:07:37 2003 UTC (8 years, 6 months ago) by bde
Branch: RELENG_3
Changes since 1.57.2.16: +20 -20
lines
Diff to previous 1.57.2.16 (colored) to branchpoint 1.57 (colored) next main 1.58 (colored)
MFC: 1.94 and 1.125 (don't use hard newlines in string literals, and fix some style bugs on the same lines). This completes making some RELENG_3 kernels work when compiled by gcc-3.3.
Revision 1.80.2.16 / (download) - annotate - [select for diffs], Tue Aug 5 07:05:39 2003 UTC (8 years, 6 months ago) by bde
Branch: RELENG_4
CVS Tags: RELENG_4_9_BP,
RELENG_4_9_0_RELEASE,
RELENG_4_9
Changes since 1.80.2.15: +19 -19
lines
Diff to previous 1.80.2.15 (colored) to branchpoint 1.80 (colored)
MFC: 1.94 and 1.125 (don't use hard newlines in string literals, and fix some style bugs on the same lines). This completes making some RELENG_4 kernels work when compiled by gcc-3.3. I intended to make more than some work, but gave up on LINT. GENERIC compliles but has not been tested at runtime.
Revision 1.125 / (download) - annotate - [select for diffs], Wed Jul 30 20:16:04 2003 UTC (8 years, 6 months ago) by bde
Branch: MAIN
Changes since 1.124: +19 -19
lines
Diff to previous 1.124 (colored)
Fixed style bugs in rev.1.94 before MFCing it (for large C asm statements, use "\n\" instead of "\" at the end of each source line, and don't use semicolons). Fixed some older style bugs on the same lines (mainly English errors in comments).
Revision 1.124 / (download) - annotate - [select for diffs], Mon Jun 2 06:43:14 2003 UTC (8 years, 8 months ago) by obrien
Branch: MAIN
Changes since 1.123: +3 -1
lines
Diff to previous 1.123 (colored)
Use __FBSDID().
Revision 1.123 / (download) - annotate - [select for diffs], Sat May 31 19:04:37 2003 UTC (8 years, 8 months ago) by phk
Branch: MAIN
Changes since 1.122: +1 -0
lines
Diff to previous 1.122 (colored)
Add missing break; Found by: FlexeLint
Revision 1.122 / (download) - annotate - [select for diffs], Wed Apr 30 12:23:58 2003 UTC (8 years, 9 months ago) by markm
Branch: MAIN
CVS Tags: RELENG_5_1_BP,
RELENG_5_1_0_RELEASE,
RELENG_5_1
Changes since 1.121: +8 -1
lines
Diff to previous 1.121 (colored)
Warns fixing. Protect against inappropriate linting, and mark GCC-specific assemble code as such (in #ifdefs). Fix an easy static variable warning while I'm here.
Revision 1.80.2.14.2.1 / (download) - annotate - [select for diffs], Mon Apr 14 14:36:19 2003 UTC (8 years, 10 months ago) by jhb
Branch: RELENG_4_8
Changes since 1.80.2.14: +1 -1
lines
Diff to previous 1.80.2.14 (colored) next main 1.80.2.15 (colored)
MFS: Fix booting on 80386 machines. CD vendor's may want to re-roll their own release to include this fix. Approved by: re (murray)
Revision 1.80.2.15 / (download) - annotate - [select for diffs], Fri Apr 11 17:06:41 2003 UTC (8 years, 10 months ago) by jhb
Branch: RELENG_4
Changes since 1.80.2.14: +1 -1
lines
Diff to previous 1.80.2.14 (colored) to branchpoint 1.80 (colored)
Revert one part of the last change so that cpu_class has a default value again. Apparently some code in pmap reads the value of this variable before it is properly initialized. That is a bug (!) but not a critical one and it is easier to make this change than hunt down that bug. This fixes booting on 80386 machines. Submitted by: Erik Trulsson <ertr1013@student.uu.se> Pointy hat to: jhb
Revision 1.121 / (download) - annotate - [select for diffs], Thu Apr 10 07:05:24 2003 UTC (8 years, 10 months ago) by wes
Branch: MAIN
Changes since 1.120: +6 -0
lines
Diff to previous 1.120 (colored)
Add a sysctl that records and reports the CPU clock rate calculated at boot. Funny how often this trivial piece of information crops up in embedded boxen. Sponsored by: St. Bernard Software
Revision 1.120 / (download) - annotate - [select for diffs], Fri Apr 4 17:29:54 2003 UTC (8 years, 10 months ago) by des
Branch: MAIN
Changes since 1.119: +1 -1
lines
Diff to previous 1.119 (colored)
Define ovbcopy() as a macro which expands to the equivalent bcopy() call, to take care of the KAME IPv6 code which needs ovbcopy() because NetBSD's bcopy() doesn't handle overlap like ours. Remove all implementations of ovbcopy(). Previously, bzero was a function pointer on i386, to save a jmp to bzero_vector. Get rid of this microoptimization as it only confuses things, adds machine-dependent code to an MD header, and doesn't really save all that much. This commit does not add my pagezero() / pagecopy() code.
Revision 1.119 / (download) - annotate - [select for diffs], Tue Mar 18 08:45:22 2003 UTC (8 years, 10 months ago) by phk
Branch: MAIN
Changes since 1.118: +0 -1
lines
Diff to previous 1.118 (colored)
Including <sys/stdint.h> is (almost?) universally only to be able to use %j in printfs, so put a newsted include in <sys/systm.h> where the printf prototype lives and save everybody else the trouble.
Revision 1.118 / (download) - annotate - [select for diffs], Thu Feb 27 20:38:48 2003 UTC (8 years, 11 months ago) by jhb
Branch: MAIN
Changes since 1.117: +3 -1
lines
Diff to previous 1.117 (colored)
Expand some #ifdef's to fix I386_CPU compile. Reported by: Andy Farkas <andyf@speednet.com.au>
Revision 1.117 / (download) - annotate - [select for diffs], Wed Jan 29 11:36:39 2003 UTC (9 years ago) by phk
Branch: MAIN
Changes since 1.116: +7 -6
lines
Diff to previous 1.116 (colored)
Make tsc_freq a 64bit quantity. Inspired by: http://www.theinquirer.net/?article=7481
Revision 1.80.2.14 / (download) - annotate - [select for diffs], Wed Jan 22 20:14:52 2003 UTC (9 years ago) by jhb
Branch: RELENG_4
CVS Tags: RELENG_4_8_BP,
RELENG_4_8_0_RELEASE
Branch point for: RELENG_4_8
Changes since 1.80.2.13: +106 -66
lines
Diff to previous 1.80.2.13 (colored) to branchpoint 1.80 (colored)
MFC: Precursors to simple hyperthreading support and sync with current: - Axe earlysetcpuclass() as it was OBE a long time ago. - Add cpu_exthigh to hold the highest supported extended cpuid. - Don't initialize cpu_class, the initial value isn't used anywhere. - Make the support for processor names in the extended cpuid information shared between the AMD and Transmeta sections and also perform it for Intel CPUs. - Support brand-indexed names for Intel CPUs. - Sync AMD 486 cpu_model's with current. - Remove duplicate and bogus docs for bits 28 and 29 of cpuid features. - Document bits 30 and 31 of cpuid features. - Display the number of logical cores on CPUs that support hyperthreading. - Make hw_instruction_sse static. - Move enable_sse()'s prototype to machine/md_var.h. - Add cpu_procinfo to hold information about this processor from cpuid 1 including count of HTT cores, brand index, local APIC ID, etc.
Revision 1.116 / (download) - annotate - [select for diffs], Wed Jan 22 17:54:12 2003 UTC (9 years ago) by jhb
Branch: MAIN
Changes since 1.115: +3 -3
lines
Diff to previous 1.115 (colored)
Rename cpuid_cpuinfo to cpu_procinfo. bde requested that I rename this variable to something in the cpu_* namespace since that's what all the other cpuid variables were named and cpu_procinfo is what I came up with. Requested by: bde
Revision 1.115 / (download) - annotate - [select for diffs], Thu Jan 9 19:59:28 2003 UTC (9 years, 1 month ago) by jhb
Branch: MAIN
Changes since 1.114: +0 -15
lines
Diff to previous 1.114 (colored)
Remove earlysetcpuclass() as it has been OBE. Suggested by: bde
Revision 1.114 / (download) - annotate - [select for diffs], Thu Jan 9 19:54:49 2003 UTC (9 years, 1 month ago) by jhb
Branch: MAIN
Changes since 1.113: +28 -2
lines
Diff to previous 1.113 (colored)
Rework part of the previous processor name changes so that we read cpu_exthigh and cpu_brand in printcpuinfo() instead of in identify_cpu(). We also only do it for known-good values of cpu_vendor which is a bit more conservative. Reviewed by: bde (mostly)
Revision 1.113 / (download) - annotate - [select for diffs], Wed Jan 8 19:16:11 2003 UTC (9 years, 1 month ago) by jhb
Branch: MAIN
Changes since 1.112: +3 -3
lines
Diff to previous 1.112 (colored)
Consistently use spaces in between arguments to strcmp(). Whitespace only.
Revision 1.112 / (download) - annotate - [select for diffs], Wed Jan 8 16:41:48 2003 UTC (9 years, 1 month ago) by jhb
Branch: MAIN
Changes since 1.111: +51 -36
lines
Diff to previous 1.111 (colored)
- Use cpu_exthigh instead of executing cpuid again to retrieve it for the print_AMD_foo() functions. - Add a brand name table for the brand index provided on Intel CPU's in %ebx after cpuid 1. - For Intel CPUs, if we don't get a processor name from the extended cpuid then use the brand index in cpuid_cpuinfo to pick a name from the brand table and copy that name into cpu_brand. - Replace the duplicated code to use the extended cpuid to replace cpu_model with the processor name in the AMD and Transmeta sections of printcpuinfo() with generic code that replaces cpu_model with cpu_brand if cpu_brand is not an empty string. We also trim leading spaces from cpu_brand prior to doing this since at least some processor names (notably those of Intel CPUs) have leading spaces in the name. - Give print_AMD_features() its own private regs[] array since printcpuinfo() doesn't use the one it has anymore.
Revision 1.111 / (download) - annotate - [select for diffs], Wed Jan 8 16:33:03 2003 UTC (9 years, 1 month ago) by jhb
Branch: MAIN
Changes since 1.110: +1 -1
lines
Diff to previous 1.110 (colored)
Bah, get the test for more than one logical CPU right so we don't bogusly claim a CPU has HT support when it lists 0 or 1 logical CPU's per physical processor.
Revision 1.110 / (download) - annotate - [select for diffs], Wed Jan 8 01:23:16 2003 UTC (9 years, 1 month ago) by jhb
Branch: MAIN
Changes since 1.109: +9 -0
lines
Diff to previous 1.109 (colored)
If the boot processor supports hyperthreading and contains more than one logical CPU, display the number of logical CPUs per physical processor underneath the list of CPU features.
Revision 1.109 / (download) - annotate - [select for diffs], Fri Jan 3 18:54:59 2003 UTC (9 years, 1 month ago) by jhb
Branch: MAIN
Changes since 1.108: +1 -1
lines
Diff to previous 1.108 (colored)
Document bit 31 of the cpuid features word as PBE (Pending Break Enable).
Revision 1.80.2.13 / (download) - annotate - [select for diffs], Mon Dec 23 18:32:05 2002 UTC (9 years, 1 month ago) by trhodes
Branch: RELENG_4
Changes since 1.80.2.12: +1 -1
lines
Diff to previous 1.80.2.12 (colored) to branchpoint 1.80 (colored)
Spell 'monintor' as 'monitor' Pointed out by: ceri
Revision 1.80.2.12 / (download) - annotate - [select for diffs], Mon Dec 23 18:10:54 2002 UTC (9 years, 1 month ago) by trhodes
Branch: RELENG_4
Changes since 1.80.2.11: +5 -3
lines
Diff to previous 1.80.2.11 (colored) to branchpoint 1.80 (colored)
MFC: revisions 1.96 && 1.97 Requested by: Peter Johnson <freebsd@bilogic.org>
Revision 1.108 / (download) - annotate - [select for diffs], Wed Sep 4 19:43:21 2002 UTC (9 years, 5 months ago) by phk
Branch: MAIN
CVS Tags: RELENG_5_0_BP,
RELENG_5_0_0_RELEASE,
RELENG_5_0
Changes since 1.107: +0 -44
lines
Diff to previous 1.107 (colored)
Change the support for AMDs ElanSC520 CPU from being a device driver to be options CPU_ELAN (NB: Soekris.com users!) It is cleaner this way. We still recognize the cpu on the host-pci bridge.
Revision 1.107 / (download) - annotate - [select for diffs], Wed Aug 14 18:07:09 2002 UTC (9 years, 5 months ago) by jmallett
Branch: MAIN
Changes since 1.106: +1 -1
lines
Diff to previous 1.106 (colored)
Document why the has_f00f_bug variable is initialised rather than placed into the BSS (so that it can be binary-patched). Inspired by: bde
Revision 1.106 / (download) - annotate - [select for diffs], Wed Jul 31 13:45:42 2002 UTC (9 years, 6 months ago) by phk
Branch: MAIN
Changes since 1.105: +1 -1
lines
Diff to previous 1.105 (colored)
The Elan SC520 MMCR is actually 16bit wide, so u_char is inconvenient.
Revision 1.105 / (download) - annotate - [select for diffs], Thu Jul 18 12:56:48 2002 UTC (9 years, 6 months ago) by phk
Branch: MAIN
Changes since 1.104: +49 -4
lines
Diff to previous 1.104 (colored)
Add initialization code for the AMD Elan sc520 which maps the MMCR into KVM and sets the i8254 frequency to the correct value.
Revision 1.80.2.11 / (download) - annotate - [select for diffs], Sun Apr 28 22:50:51 2002 UTC (9 years, 9 months ago) by dwmalone
Branch: RELENG_4
CVS Tags: RELENG_4_7_BP,
RELENG_4_7_0_RELEASE,
RELENG_4_7,
RELENG_4_6_BP,
RELENG_4_6_2_RELEASE,
RELENG_4_6_1_RELEASE,
RELENG_4_6_0_RELEASE,
RELENG_4_6
Changes since 1.80.2.10: +0 -11
lines
Diff to previous 1.80.2.10 (colored) to branchpoint 1.80 (colored)
MFC (identcpu.c 1.101, cpufunc.h 1.108 and 1.120): Move do_cpuid() from a identcpu.c into cpufunc.h and make style match surounding code. Gcc constraints still need to be fixed.
Revision 1.104 / (download) - annotate - [select for diffs], Sat Apr 27 18:13:35 2002 UTC (9 years, 9 months ago) by alc
Branch: MAIN
Changes since 1.103: +8 -1
lines
Diff to previous 1.103 (colored)
For what it's worth, fix the compilation of an I386_CPU-only kernel now that certain warnings are fatal.
Revision 1.80.2.10 / (download) - annotate - [select for diffs], Mon Mar 25 12:51:31 2002 UTC (9 years, 10 months ago) by nyan
Branch: RELENG_4
Changes since 1.80.2.9: +28 -24
lines
Diff to previous 1.80.2.9 (colored) to branchpoint 1.80 (colored)
MFC: revision 1.100 (Cosmetic changes).
Revision 1.103 / (download) - annotate - [select for diffs], Mon Mar 4 18:45:56 2002 UTC (9 years, 11 months ago) by iwasaki
Branch: MAIN
Changes since 1.102: +70 -0
lines
Diff to previous 1.102 (colored)
Add generalized power profile code. This makes other power-management system (APM for now) to be able to generate power profile change events (ie. AC-line status changes), and other kernel components, not only the ACPI components, can be notified the events. - move subroutines in acpi_powerprofile.c (removed) to kern/subr_power.c - call power_profile_set_state() also from APM driver when AC-line status changes - add call-back function for Crusoe LongRun controlling on power profile changes for a example
Revision 1.80.2.9 / (download) - annotate - [select for diffs], Wed Feb 20 14:19:28 2002 UTC (9 years, 11 months ago) by cjc
Branch: RELENG_4
Changes since 1.80.2.8: +1 -1
lines
Diff to previous 1.80.2.8 (colored) to branchpoint 1.80 (colored)
Fix typo in comment. PR: i386/35114 Submitted by: Gavin Atkinson <gavin.atkinson@ury.york.ac.uk>
Revision 1.102 / (download) - annotate - [select for diffs], Wed Feb 20 14:15:58 2002 UTC (9 years, 11 months ago) by cjc
Branch: MAIN
Changes since 1.101: +2 -2
lines
Diff to previous 1.101 (colored)
Fix typos in some comments. PR: i386/35114 Submitted by: Gavin Atkinson <gavin.atkinson@ury.york.ac.uk>
Revision 1.101 / (download) - annotate - [select for diffs], Tue Feb 12 21:06:43 2002 UTC (10 years ago) by dwmalone
Branch: MAIN
Changes since 1.100: +0 -11
lines
Diff to previous 1.100 (colored)
Move do_cpuid() from a identcpu.c into cpufunc.h.
Revision 1.80.2.8 / (download) - annotate - [select for diffs], Tue Feb 12 03:17:12 2002 UTC (10 years ago) by kato
Branch: RELENG_4
Changes since 1.80.2.7: +6 -4
lines
Diff to previous 1.80.2.7 (colored) to branchpoint 1.80 (colored)
MFC: revision 1.99 (recognize VIA C3 Samuel 2).
Revision 1.100 / (download) - annotate - [select for diffs], Sun Feb 10 11:23:14 2002 UTC (10 years ago) by kato
Branch: MAIN
Changes since 1.99: +28 -24
lines
Diff to previous 1.99 (colored)
Cosmetic changes: - Collected i486 identification codes in one place like 586 and 686. - Merged two cases (0x470 and 0x490) for `Enhanced Am486DX4 Write-Back.' - Replaced `unknown' into `Unknown'. Submitted by: chi@bd.mbn.or.jp (Chiharu Shibata)
Revision 1.99 / (download) - annotate - [select for diffs], Sat Feb 9 05:18:01 2002 UTC (10 years ago) by kato
Branch: MAIN
Changes since 1.98: +6 -4
lines
Diff to previous 1.98 (colored)
Recognize VIA C3 Samuel 2. MFC after: 3 days
Revision 1.98 / (download) - annotate - [select for diffs], Tue Jan 22 01:28:32 2002 UTC (10 years ago) by peter
Branch: MAIN
Changes since 1.97: +2 -2
lines
Diff to previous 1.97 (colored)
List bit 18 (reserved, apparently present on thunderbird cpus) and bit 19 (athlon XP/MP rev 0x662 and later) for amd_features. Submitted by: dwcjr
Revision 1.97 / (download) - annotate - [select for diffs], Wed Jan 16 02:22:19 2002 UTC (10 years ago) by peter
Branch: MAIN
Changes since 1.96: +3 -3
lines
Diff to previous 1.96 (colored)
Change <b28> to HTT (Hyperthreading technology). If this flag is set then cpuid with %eax=1 will return a logical cpu count in bits 16-23 of %ebx. Bit 29 is actually 'TM' according to AP-485. This signifies the presence of the thermal control circuit (which I believe can slow the clock down to reduce core temperature).
Revision 1.96 / (download) - annotate - [select for diffs], Fri Nov 30 11:57:23 2001 UTC (10 years, 2 months ago) by peter
Branch: MAIN
Changes since 1.95: +1 -1
lines
Diff to previous 1.95 (colored)
cpuid bit 30 is 'IA64', for when you're running in i386 mode on an ia64 cpu. (This is for either userland apps running in i386 mode on an ia64 OS, or when the cpu is in i386 legacy mode running an i386 OS).
Revision 1.80.2.7 / (download) - annotate - [select for diffs], Thu Oct 18 04:05:14 2001 UTC (10 years, 3 months ago) by jdp
Branch: RELENG_4
CVS Tags: RELENG_4_5_BP,
RELENG_4_5_0_RELEASE,
RELENG_4_5
Changes since 1.80.2.6: +4 -9
lines
Diff to previous 1.80.2.6 (colored) to branchpoint 1.80 (colored)
MFC 1.94 -> 1.95: Fix the cpuid asm statement so it works at -O2. Also, replace the .byte directive with the "cpuid" mnemonic, since the assembler supports it now.
Revision 1.95 / (download) - annotate - [select for diffs], Fri Oct 12 16:49:28 2001 UTC (10 years, 4 months ago) by jdp
Branch: MAIN
Changes since 1.94: +4 -9
lines
Diff to previous 1.94 (colored)
Correct the input/output/clobber specifications for the cpuid instruction. Stefan Keller <dres@earth.serd.org> noticed that CPU identification was broken when compiled with -O2, and tracked it down to the asm statement, which was storing values into memory without specifying that memory was modified. He submitted a patch which added "memory" as a clobber, but I refined it further to arrive at this version. MFC after: 3 days
Revision 1.94 / (download) - annotate - [select for diffs], Mon Sep 10 04:22:20 2001 UTC (10 years, 5 months ago) by peter
Branch: MAIN
CVS Tags: KSE_PRE_MILESTONE_2,
KSE_MILESTONE_2
Changes since 1.93: +20 -20
lines
Diff to previous 1.93 (colored)
gcc-3 has objections about the bluetrap6 and bluetrap13 inline asm functions. Apparently multi-line string asm arguments are deprecated.
Revision 1.80.2.6 / (download) - annotate - [select for diffs], Thu Jul 19 09:12:07 2001 UTC (10 years, 6 months ago) by kato
Branch: RELENG_4
CVS Tags: RELENG_4_4_BP,
RELENG_4_4_0_RELEASE,
RELENG_4_4
Changes since 1.80.2.5: +2 -1
lines
Diff to previous 1.80.2.5 (colored) to branchpoint 1.80 (colored)
MFC: Recoginize Tualatin core (1.92.)
Revision 1.80.2.5 / (download) - annotate - [select for diffs], Wed Jul 11 14:22:13 2001 UTC (10 years, 7 months ago) by iwasaki
Branch: RELENG_4
Changes since 1.80.2.4: +254 -2
lines
Diff to previous 1.80.2.4 (colored) to branchpoint 1.80 (colored)
MFC: Add code to detect Transmeta Crusoe cpus (1.90->1.91) and
LongRun support (1.92->1.93).
Okayed by: dfr
Revision 1.93 / (download) - annotate - [select for diffs], Tue Jul 3 10:03:24 2001 UTC (10 years, 7 months ago) by iwasaki
Branch: MAIN
Changes since 1.92: +199 -1
lines
Diff to previous 1.92 (colored)
Add Transmeta Crusoe LongRun support. Submitted by: Tamotsu HATTORI <athlete@kta.att.ne.jp> Reviewed by: arch@ folks MFC after: 1 week
Revision 1.92 / (download) - annotate - [select for diffs], Tue Jun 26 03:02:30 2001 UTC (10 years, 7 months ago) by kato
Branch: MAIN
Changes since 1.91: +2 -1
lines
Diff to previous 1.91 (colored)
Recognize FC-PGA2 Pentium III (Tualatin).
Revision 1.91 / (download) - annotate - [select for diffs], Mon Jun 25 15:11:33 2001 UTC (10 years, 7 months ago) by dfr
Branch: MAIN
Changes since 1.90: +56 -3
lines
Diff to previous 1.90 (colored)
Add code to detect Transmeta Crusoe cpus.
Revision 1.90 / (download) - annotate - [select for diffs], Tue Jan 16 09:10:32 2001 UTC (11 years ago) by peter
Branch: MAIN
Changes since 1.89: +7 -4
lines
Diff to previous 1.89 (colored)
Stop doing runtime checking on i386 cpus for cpu class. The cpu is
slow enough as it is, without having to constantly check that it really
is an i386 still. It was possible to compile out the conditionals for
faster cpus by leaving out 'I386_CPU', but it was not possible to
unconditionally compile for the i386. You got the runtime checking whether
you wanted it or not. This makes I386_CPU mutually exclusive with the
other cpu types, and tidies things up a little in the process.
Reviewed by: alfred, markm, phk, benno, jlemon, jhb, jake, grog, msmith,
jasone, dcs, des (and a bunch more people who encouraged it)
Revision 1.89 / (download) - annotate - [select for diffs], Tue Nov 21 20:16:47 2000 UTC (11 years, 2 months ago) by markm
Branch: MAIN
Changes since 1.88: +2 -2
lines
Diff to previous 1.88 (colored)
Assembler fixes. Fix opcodes that were typed as ".byte 0xNN, 0xMM" when an older assembler could not recognise the newer Pentium instructions. Reviewed by: jhb
Revision 1.88 / (download) - annotate - [select for diffs], Sun Oct 29 13:56:41 2000 UTC (11 years, 3 months ago) by phk
Branch: MAIN
Changes since 1.87: +1 -2
lines
Diff to previous 1.87 (colored)
Remove unneeded #include <sys/proc.h> lines.
Revision 1.57.2.16 / (download) - annotate - [select for diffs], Mon Oct 2 13:49:25 2000 UTC (11 years, 4 months ago) by asmodai
Branch: RELENG_3
Changes since 1.57.2.15: +20 -13
lines
Diff to previous 1.57.2.15 (colored) to branchpoint 1.57 (colored)
MFC: - Pentium 4 recognition code - Descriptions of some features
Revision 1.80.2.4 / (download) - annotate - [select for diffs], Sat Sep 30 03:32:21 2000 UTC (11 years, 4 months ago) by ps
Branch: RELENG_4
CVS Tags: RELENG_4_3_BP,
RELENG_4_3_0_RELEASE,
RELENG_4_3,
RELENG_4_2_0_RELEASE
Changes since 1.80.2.3: +16 -11
lines
Diff to previous 1.80.2.3 (colored) to branchpoint 1.80 (colored)
MFC: Pentium4 support.
Revision 1.87 / (download) - annotate - [select for diffs], Fri Sep 29 04:53:00 2000 UTC (11 years, 4 months ago) by peter
Branch: MAIN
Changes since 1.86: +11 -11
lines
Diff to previous 1.86 (colored)
Fill in some more missing bits from cpu_features according to the Intel Pentium4 cpuid docs.
Revision 1.86 / (download) - annotate - [select for diffs], Fri Sep 29 04:38:35 2000 UTC (11 years, 4 months ago) by peter
Branch: MAIN
Changes since 1.85: +6 -1
lines
Diff to previous 1.85 (colored)
First shot at identifying the Pentum 4 acording to our reading of the the cpu_id extensions in the Intel docs. There is more info available. See the following URL for more details. http://developer.intel.com/design/processor/future/manuals/CPUID_Supplement.htm Requested by: Intel
Revision 1.85 / (download) - annotate - [select for diffs], Wed Sep 27 11:33:31 2000 UTC (11 years, 4 months ago) by asmodai
Branch: MAIN
Changes since 1.84: +2 -2
lines
Diff to previous 1.84 (colored)
Fix spelling of Katmai [Katami].
Revision 1.80.2.3 / (download) - annotate - [select for diffs], Wed Sep 27 11:32:54 2000 UTC (11 years, 4 months ago) by asmodai
Branch: RELENG_4
Changes since 1.80.2.2: +25 -21
lines
Diff to previous 1.80.2.2 (colored) to branchpoint 1.80 (colored)
MFC: Add some features which will now be recognised. Add documentation comments. Fix Katmai spelling.
Revision 1.57.2.15 / (download) - annotate - [select for diffs], Wed Sep 27 11:20:02 2000 UTC (11 years, 4 months ago) by asmodai
Branch: RELENG_3
Changes since 1.57.2.14: +46 -42
lines
Diff to previous 1.57.2.14 (colored) to branchpoint 1.57 (colored)
MFC: Add a ton of features which will now be recognised. Add documentation comments. Add sysctl descriptions.
Revision 1.57.2.14 / (download) - annotate - [select for diffs], Tue Sep 26 15:06:08 2000 UTC (11 years, 4 months ago) by asmodai
Branch: RELENG_3
Changes since 1.57.2.13: +2 -1
lines
Diff to previous 1.57.2.13 (colored) to branchpoint 1.57 (colored)
MFC: Recognize new Pentium III Xeon (stepping A0).
Revision 1.80.2.2 / (download) - annotate - [select for diffs], Tue Sep 26 09:02:23 2000 UTC (11 years, 4 months ago) by kato
Branch: RELENG_4
Changes since 1.80.2.1: +2 -1
lines
Diff to previous 1.80.2.1 (colored) to branchpoint 1.80 (colored)
MFC: Recognize new Pentium III Xeon (stepping A0).
Revision 1.84 / (download) - annotate - [select for diffs], Tue Sep 26 08:59:55 2000 UTC (11 years, 4 months ago) by kato
Branch: MAIN
Changes since 1.83: +2 -1
lines
Diff to previous 1.83 (colored)
Recognize new Pentium III Xeon (stepping A0). PR: 21233 Submitted by: ade
Revision 1.83 / (download) - annotate - [select for diffs], Thu Sep 7 01:32:43 2000 UTC (11 years, 5 months ago) by jasone
Branch: MAIN
Changes since 1.82: +4 -1
lines
Diff to previous 1.82 (colored)
Major update to the way synchronization is done in the kernel. Highlights include: * Mutual exclusion is used instead of spl*(). See mutex(9). (Note: The alpha port is still in transition and currently uses both.) * Per-CPU idle processes. * Interrupts are run in their own separate kernel threads and can be preempted (i386 only). Partially contributed by: BSDi (BSD/OS) Submissions by (at least): cp, dfr, dillon, grog, jake, jhb, sheldonh
Revision 1.57.2.13 / (download) - annotate - [select for diffs], Wed Jun 14 13:02:54 2000 UTC (11 years, 8 months ago) by kato
Branch: RELENG_3
CVS Tags: RELENG_3_5_0_RELEASE
Changes since 1.57.2.12: +2 -2
lines
Diff to previous 1.57.2.12 (colored) to branchpoint 1.57 (colored)
MFC: Celeron recognition (rev. 1.82).
Revision 1.80.2.1 / (download) - annotate - [select for diffs], Wed Jun 14 13:00:25 2000 UTC (11 years, 8 months ago) by kato
Branch: RELENG_4
CVS Tags: RELENG_4_1_1_RELEASE,
RELENG_4_1_0_RELEASE
Changes since 1.80: +2 -2
lines
Diff to previous 1.80 (colored)
MFC: Celeron recognition (rev. 1.82).
Revision 1.82 / (download) - annotate - [select for diffs], Tue Jun 13 12:33:45 2000 UTC (11 years, 8 months ago) by kato
Branch: MAIN
CVS Tags: PRE_SMPNG
Changes since 1.81: +2 -2
lines
Diff to previous 1.81 (colored)
Recognize Coppermine Celeron processors whose CPU ID = 0x68?. They were recognized as "Pentium III/Pentium III Xeon."
Revision 1.81 / (download) - annotate - [select for diffs], Wed May 3 18:07:30 2000 UTC (11 years, 9 months ago) by dwhite
Branch: MAIN
Changes since 1.80: +24 -20
lines
Diff to previous 1.80 (colored)
I mentioned yesterday that I could use some work, and Kelly says, "Commit my PRs!" So here I go. Add definitions for some of the AMD CPU feature bits. Also add a comment on where to find the rest of them. This is a purely cosmetic change. PR: i386/14438 Submitted by: Kelly Yancey <kbyanc@egroups.net>
Revision 1.57.2.12 / (download) - annotate - [select for diffs], Wed Mar 22 11:21:16 2000 UTC (11 years, 10 months ago) by patrick
Branch: RELENG_3
Changes since 1.57.2.11: +1 -5
lines
Diff to previous 1.57.2.11 (colored) to branchpoint 1.57 (colored)
MFC: Display CPU (BSP) clock speed on SMP systems. (-CURRENT diff 1.76)
Reviewed by: green
Tested by: Brandon D. Valentine <bandix@looksharp.net>
Tod Luginbuhl <tod@science-guy.npt.nuwc.navy.mil>
Revision 1.57.2.11 / (download) - annotate - [select for diffs], Wed Mar 22 05:27:22 2000 UTC (11 years, 10 months ago) by nyan
Branch: RELENG_3
Changes since 1.57.2.10: +5 -12
lines
Diff to previous 1.57.2.10 (colored) to branchpoint 1.57 (colored)
MFC: Simplify messages of Pentium II, Pentium II Xeon, Celeron, Pentium III
and Pentium III Xeon CPUs.
Revision 1.57.2.10 / (download) - annotate - [select for diffs], Wed Feb 2 03:50:19 2000 UTC (12 years ago) by bde
Branch: RELENG_3
Changes since 1.57.2.9: +3 -1
lines
Diff to previous 1.57.2.9 (colored) to branchpoint 1.57 (colored)
MFC: fixes for profiling of elf kernels. See the commit logs on 1999/05/10 for identcpu.c and on 1999/05/6 for everything else. Unlike in -current, no additional fixes are needed for high resolution profiling.
Revision 1.80 / (download) - annotate - [select for diffs], Sat Jan 29 07:49:02 2000 UTC (12 years ago) by kato
Branch: MAIN
CVS Tags: RELENG_4_BP,
RELENG_4_0_0_RELEASE
Branch point for: RELENG_4
Changes since 1.79: +5 -12
lines
Diff to previous 1.79 (colored)
Simplify messages of Pentium II, Pentium II Xeon, Celeron, Pentium III and Pentium III Xeon CPUs. If a CPU is one of Pentium II, Pentium II Xeon and Celeron, the message is always "Pentium II/Pentium II Xeon/Celeron". If a CPU is one of Pentium III and Pentium III Xeon, the message is always "Pentium III/Pentium III Xeon".
Revision 1.57.2.9 / (download) - annotate - [select for diffs], Sat Jan 15 06:29:41 2000 UTC (12 years ago) by tanimura
Branch: RELENG_3
Changes since 1.57.2.8: +5 -1
lines
Diff to previous 1.57.2.8 (colored) to branchpoint 1.57 (colored)
MFC: Add P-III(Coppermine).
Revision 1.79 / (download) - annotate - [select for diffs], Sat Jan 15 06:29:03 2000 UTC (12 years ago) by tanimura
Branch: MAIN
Changes since 1.78: +5 -1
lines
Diff to previous 1.78 (colored)
A processor with the CPUID of 0x?8? is Pentium III. (aka Coppermine) Noticed by: Satoshi Sawada <k-sawata@gnoc2.comminet.or.jp> Reviewd by: Takuma Yamada <fuzzy2@st.rim.or.jp>
Revision 1.78 / (download) - annotate - [select for diffs], Sun Oct 24 23:36:20 1999 UTC (12 years, 3 months ago) by alc
Branch: MAIN
Changes since 1.77: +3 -3
lines
Diff to previous 1.77 (colored)
Add text for the Athlon's MMX and 3DNow! (DSP) instruction extensions to print_AMD_features.
Revision 1.77 / (download) - annotate - [select for diffs], Thu Oct 14 13:59:52 1999 UTC (12 years, 4 months ago) by kato
Branch: MAIN
Changes since 1.76: +3 -3
lines
Diff to previous 1.76 (colored)
Recognize Pentium II w/ CPUID = 0x6XX and Pentium III Xeon w/ CPUID = 0x7XX. Pointed out by: Brian Somers <brian@Awfulhak.org>
Revision 1.76 / (download) - annotate - [select for diffs], Wed Sep 22 21:21:53 1999 UTC (12 years, 4 months ago) by luoqi
Branch: MAIN
Changes since 1.75: +1 -5
lines
Diff to previous 1.75 (colored)
Display CPU (BSP) clock speed on SMP systems.
Revision 1.57.2.8 / (download) - annotate - [select for diffs], Fri Sep 10 20:47:22 1999 UTC (12 years, 5 months ago) by phk
Branch: RELENG_3
CVS Tags: RELENG_3_4_0_RELEASE,
RELENG_3_3_0_RELEASE
Changes since 1.57.2.7: +2 -1
lines
Diff to previous 1.57.2.7 (colored) to branchpoint 1.57 (colored)
MFC: tsc is not suitable for timecounting on WinChip C6 Submitted by: IMAI Takeshi <take-i@ceres.dti.ne.jp> Reviewed by: phk Approved by: jkh
Revision 1.75 / (download) - annotate - [select for diffs], Fri Sep 10 20:45:50 1999 UTC (12 years, 5 months ago) by phk
Branch: MAIN
Changes since 1.74: +2 -1
lines
Diff to previous 1.74 (colored)
System clock don't update, because C6's TSC stop count up when run HALT instruction. PR: 13683 Submitted by: IMAI Takeshi <take-i@ceres.dti.ne.jp> Reviewed by: phk
Revision 1.74 / (download) - annotate - [select for diffs], Fri Sep 10 15:47:54 1999 UTC (12 years, 5 months ago) by peter
Branch: MAIN
Changes since 1.73: +18 -18
lines
Diff to previous 1.73 (colored)
Add text for the PN (Processor serial number) and XMM (extended SIMD/MMX2/ support), as well as a bunch of comments for what the various bits mean (those that I remember anyway).
Revision 1.7.2.19 / (download) - annotate - [select for diffs], Sun Sep 5 08:11:07 1999 UTC (12 years, 5 months ago) by peter
Branch: RELENG_2_2
Changes since 1.7.2.18: +1 -1
lines
Diff to previous 1.7.2.18 (colored) to branchpoint 1.7 (colored) next main 1.8 (colored)
$Id$ -> $FreeBSD$
Revision 1.57.2.7 / (download) - annotate - [select for diffs], Sun Aug 29 16:05:41 1999 UTC (12 years, 5 months ago) by peter
Branch: RELENG_3
Changes since 1.57.2.6: +1 -1
lines
Diff to previous 1.57.2.6 (colored) to branchpoint 1.57 (colored)
$Id$ -> $FreeBSD$
Revision 1.73 / (download) - annotate - [select for diffs], Sat Aug 28 00:43:44 1999 UTC (12 years, 5 months ago) by peter
Branch: MAIN
Changes since 1.72: +1 -1
lines
Diff to previous 1.72 (colored)
$Id$ -> $FreeBSD$
Revision 1.57.2.6 / (download) - annotate - [select for diffs], Fri Aug 27 08:09:04 1999 UTC (12 years, 5 months ago) by kato
Branch: RELENG_3
Changes since 1.57.2.5: +15 -1
lines
Diff to previous 1.57.2.5 (colored) to branchpoint 1.57 (colored)
MFC: IBM BlueLightning CPU detection (revision 1.72).
Revision 1.72 / (download) - annotate - [select for diffs], Fri Aug 20 09:31:18 1999 UTC (12 years, 5 months ago) by kato
Branch: MAIN
Changes since 1.71: +15 -1
lines
Diff to previous 1.71 (colored)
There may exist two kinds of IBM BlueLightning CPU. One is that 5/2 test does not change undefined flag like Cyrix CPUs. Another is that 5/2 test changes undefined flag like Intel CPUs. Latter one could not be detected and was recognized 486DX CPU. To solve this, finishidentcpu() calls identblue() when cpu_vendor is null string (that is, CPUID instruction is not supported) and cpu == CPU_486. Tests have been done on IBM BlueLightning CPUs, i486SX and i486DX.
Revision 1.57.2.5 / (download) - annotate - [select for diffs], Tue Jul 6 17:21:48 1999 UTC (12 years, 7 months ago) by green
Branch: RELENG_3
Changes since 1.57.2.4: +2 -2
lines
Diff to previous 1.57.2.4 (colored) to branchpoint 1.57 (colored)
0ff0 -> 0xff0. Sorry about that. Noticed by: cracauer Pointy hat to: green
Revision 1.71 / (download) - annotate - [select for diffs], Tue Jul 6 13:23:56 1999 UTC (12 years, 7 months ago) by peter
Branch: MAIN
Changes since 1.70: +2 -2
lines
Diff to previous 1.70 (colored)
Quieten gcc paranoia.
Revision 1.70 / (download) - annotate - [select for diffs], Tue Jul 6 12:42:26 1999 UTC (12 years, 7 months ago) by peter
Branch: MAIN
Changes since 1.69: +2 -2
lines
Diff to previous 1.69 (colored)
Typo: s/0ff0/0xff0/
Revision 1.57.2.4 / (download) - annotate - [select for diffs], Tue Jul 6 06:49:47 1999 UTC (12 years, 7 months ago) by green
Branch: RELENG_3
Changes since 1.57.2.3: +81 -12
lines
Diff to previous 1.57.2.3 (colored) to branchpoint 1.57 (colored)
MFC some i386-family-CPU changes.
Revision 1.69 / (download) - annotate - [select for diffs], Tue Jul 6 06:25:38 1999 UTC (12 years, 7 months ago) by green
Branch: MAIN
Changes since 1.68: +14 -1
lines
Diff to previous 1.68 (colored)
Add Centaur/IDT WinChip support. Why in the world do people put breaks at the end of a switch's default case?
Revision 1.68 / (download) - annotate - [select for diffs], Tue Jul 6 05:25:41 1999 UTC (12 years, 7 months ago) by green
Branch: MAIN
Changes since 1.67: +52 -47
lines
Diff to previous 1.67 (colored)
I made some cleanups, rearranged things a bit, and made AMD Features default printing on CPUs that have it. If there are no objections, I'll MFC all recent changes (harmless, really) to 3.2 and PAO.
Revision 1.67 / (download) - annotate - [select for diffs], Mon Jul 5 02:28:21 1999 UTC (12 years, 7 months ago) by green
Branch: MAIN
Changes since 1.66: +2 -2
lines
Diff to previous 1.66 (colored)
Add an extra space to " AMD Features=" to make it line up well.
Revision 1.66 / (download) - annotate - [select for diffs], Mon Jul 5 02:27:32 1999 UTC (12 years, 7 months ago) by green
Branch: MAIN
Changes since 1.65: +54 -4
lines
Diff to previous 1.65 (colored)
K6-III CPUs are now case:d in the appropriate switch; also, in print_AMD_info(), L2 internal cache is shown, as are AMD's special CPUID infos: CPU: AMD-K6(tm) 3D processor (350.81-MHz 586-class CPU) Origin = "AuthenticAMD" Id = 0x58c Stepping=12 Features=0x8021bf<FPU,VME,DE,PSE,TSC,MSR,MCE,CX8,PGE,MMX> AMD Features=0x808029bf<FPU,VME,DE,PSE,TSC,MSR,MCE,CX8,SYSCALL,PGE,MMX,3DNow!> PR: kern/12512 Submitted by: Louis A. Mamakos <louie@TransSys.COM>
Revision 1.57.2.3 / (download) - annotate - [select for diffs], Fri Jun 25 03:05:48 1999 UTC (12 years, 7 months ago) by green
Branch: RELENG_3
Changes since 1.57.2.2: +12 -2
lines
Diff to previous 1.57.2.2 (colored) to branchpoint 1.57 (colored)
MFC: Rise mP6 support requires an addition to identcpu.c, and a workaround
to the read-only (write -> GPF) TSC. We no longer zero the TSC at
boot.
Reviewed by: msmith
Revision 1.57.2.2 / (download) - annotate - [select for diffs], Thu Jun 24 20:16:34 1999 UTC (12 years, 7 months ago) by jlemon
Branch: RELENG_3
Changes since 1.57.2.1: +2 -2
lines
Diff to previous 1.57.2.1 (colored) to branchpoint 1.57 (colored)
MFC: rev 1.65, cyrix WT_ALLOC fix.
Revision 1.65 / (download) - annotate - [select for diffs], Thu Jun 24 20:08:56 1999 UTC (12 years, 7 months ago) by jlemon
Branch: MAIN
Changes since 1.64: +2 -2
lines
Diff to previous 1.64 (colored)
Only include AMD wt_alloc routines if I586_CPU is defined. Fixes CPU_WT_ALLOC for cyrix chips. Submitted by: "Brian Smith" <dbsoft@technologist.com>
Revision 1.64 / (download) - annotate - [select for diffs], Thu Jun 24 03:47:54 1999 UTC (12 years, 7 months ago) by green
Branch: MAIN
Changes since 1.63: +12 -2
lines
Diff to previous 1.63 (colored)
This commit gives support for the Rise mP6 CPU. It has two changes: 1. Rise is recognized in identdcpu.c. 2. The TSC is not written to. A workaround for the CPU bug is being applied to clock.c (the bug being that the mP6 has TSC enabled in its CPUID-capabilities, but it only supports reading it. If we try to write to it (MSR 16), a GPF occurs.) The new behavior is that FreeBSD will _not_ zero the TSC. Instead, we do a bit of 64-bit arithmetic. Reviewed by: msmith Obtained from: unfurl & msmith
Revision 1.63 / (download) - annotate - [select for diffs], Sat May 29 06:57:38 1999 UTC (12 years, 8 months ago) by phk
Branch: MAIN
Changes since 1.62: +2 -1
lines
Diff to previous 1.62 (colored)
Stop the TSC from being used as timecounter on K5/step0 machines.
Revision 1.62 / (download) - annotate - [select for diffs], Mon May 10 10:51:25 1999 UTC (12 years, 9 months ago) by bde
Branch: MAIN
Changes since 1.61: +3 -1
lines
Diff to previous 1.61 (colored)
[Forgot to commit this in the batch a few days ago.] Fixed profiling of elf kernels. Made high resolution profiling compile for elf kernels (it is broken for all kernels due to lack of egcs support). Renaming of many assembler labels is avoided by declaring by declaring the labels that need to be visible to gprof as having type "function" and depending on the elf version of gprof being zealous about discarding the others. A few type declarations are still missing, mainly for SMP. PR: 9413 Submitted by: Assar Westerlund <assar@sics.se> (initial parts)
Revision 1.61 / (download) - annotate - [select for diffs], Mon May 3 23:57:13 1999 UTC (12 years, 9 months ago) by billf
Branch: MAIN
Changes since 1.60: +5 -3
lines
Diff to previous 1.60 (colored)
Add sysctl descriptions to many SYSCTL_XXXs PR: kern/11197 Submitted by: Adrian Chadd <adrian@FreeBSD.org> Reviewed by: billf(spelling/style/minor nits) Looked at by: bde(style)
Revision 1.60 / (download) - annotate - [select for diffs], Wed Mar 10 20:42:00 1999 UTC (12 years, 11 months ago) by roberto
Branch: MAIN
CVS Tags: PRE_VFS_BIO_NFS_PATCH,
PRE_SMP_VMSHARE,
PRE_NEWBUS,
POST_VFS_BIO_NFS_PATCH,
POST_SMP_VMSHARE,
POST_NEWBUS
Changes since 1.59: +3 -3
lines
Diff to previous 1.59 (colored)
Fix two tests against hex. values for CPUID. PR: i386/10050 Submitted by: Kevin Day <toasty@dragondata.com>
Revision 1.59 / (download) - annotate - [select for diffs], Sat Feb 20 19:46:39 1999 UTC (12 years, 11 months ago) by roberto
Branch: MAIN
Changes since 1.58: +2 -2
lines
Diff to previous 1.58 (colored)
Bit 24 of the Feature Flag is FXSR (for Fast FP Save and Restore). Reminded by: Francis Dupont <Francis.Dupont@inria.fr>
Revision 1.57.2.1 / (download) - annotate - [select for diffs], Sat Feb 6 16:20:17 1999 UTC (13 years ago) by kato
Branch: RELENG_3
CVS Tags: RELENG_3_2_PAO_BP,
RELENG_3_2_PAO,
RELENG_3_2_0_RELEASE,
RELENG_3_1_0_RELEASE
Changes since 1.57: +11 -2
lines
Diff to previous 1.57 (colored)
MFC: Pentium II Xeon, Celeron and Pentium III recognition. OKed by: jkh
Revision 1.58 / (download) - annotate - [select for diffs], Thu Feb 4 16:48:25 1999 UTC (13 years ago) by kato
Branch: MAIN
Changes since 1.57: +11 -2
lines
Diff to previous 1.57 (colored)
Recognize Pentium II Xeon, Celeron and Pentium III cpus. Because CPU names are printed on their packages and shown by BIOS, kernel does not need to show details. PR: 8751, 9320 and 9463
Revision 1.57 / (download) - annotate - [select for diffs], Sat Jan 16 13:41:33 1999 UTC (13 years ago) by kato
Branch: MAIN
CVS Tags: RELENG_3_BP
Branch point for: RELENG_3
Changes since 1.56: +20 -17
lines
Diff to previous 1.56 (colored)
There are two models of AMD K6-2 Model 8 (c.f. AMD's document), so the CPU stepping must be checked. Also, fixed print_AMD_info. Submitted by: Akio Morita <amorita@meadow.scphys.kyoto-u.ac.jp>
Revision 1.56 / (download) - annotate - [select for diffs], Sat Jan 9 13:07:18 1999 UTC (13 years, 1 month ago) by bde
Branch: MAIN
Changes since 1.55: +8 -8
lines
Diff to previous 1.55 (colored)
Don't put operands in clobber lists, since this is dubious for old versions of gcc and broken for current versions of egcs. Cleaned up the asm statement for do_cpuid() a little. Submitted by: "John S. Dyson" <dyson@iquest.net> but rewritten by me
Revision 1.55 / (download) - annotate - [select for diffs], Fri Jan 8 16:29:56 1999 UTC (13 years, 1 month ago) by bde
Branch: MAIN
Changes since 1.54: +4 -5
lines
Diff to previous 1.54 (colored)
Moved declarations related to copying and zeroing to the right place.
Revision 1.54 / (download) - annotate - [select for diffs], Sun Dec 27 23:23:26 1998 UTC (13 years, 1 month ago) by msmith
Branch: MAIN
Changes since 1.53: +19 -6
lines
Diff to previous 1.53 (colored)
From the submitter: CPU_WT_ALLOC does not work correctly for K6-2s of model 8+ and probably K6-3s (when they appear on the market soon). In addition, print_AMD_info() incorrectly printfs write allocation's size. I've fixed them, so they now Do The Right Thing, and added a "NO_MEMORY_HOLE" option to easily allow 15-16mb range handling for us K6 and K6-2 users. Submitted by: Brian Feldman <green@unixhelp.org>
Revision 1.53 / (download) - annotate - [select for diffs], Sat Dec 5 16:30:55 1998 UTC (13 years, 2 months ago) by kato
Branch: MAIN
Changes since 1.52: +20 -1
lines
Diff to previous 1.52 (colored)
Print out information for write-allocate of AMD CPUs. Submitted by: Akio Morita <amorita@meadow.scphys.kyoto-u.ac.jp>
Revision 1.52 / (download) - annotate - [select for diffs], Tue Oct 6 13:16:23 1998 UTC (13 years, 4 months ago) by kato
Branch: MAIN
CVS Tags: RELENG_3_0_0_RELEASE
Changes since 1.51: +25 -5
lines
Diff to previous 1.51 (colored)
- Implement enabling write allocate on AMD K5/K6/K6-2 cpus. The code was originaly contributed by Kelly Yancey <kbyanc@freedomnet.com> in PR i386/6269 and revised by Akio Morita <amorita@meadow.scphys.kyoto-u.ac.jp> and me. Test was performed by Akio Morita and Toshiomi Moriki <moriki@db.is.kyushu-u.ac.jp>. - Fix stylistic bug in identcpu.c. - Update copyright in initcpu.c - Fix typo in LINT. PR: 6269 and 6270
Revision 1.51 / (download) - annotate - [select for diffs], Sat Jul 11 07:45:28 1998 UTC (13 years, 7 months ago) by bde
Branch: MAIN
Changes since 1.50: +7 -7
lines
Diff to previous 1.50 (colored)
Fixed printf format errors.
Revision 1.50 / (download) - annotate - [select for diffs], Sat Jul 11 05:59:34 1998 UTC (13 years, 7 months ago) by bde
Branch: MAIN
Changes since 1.49: +8 -8
lines
Diff to previous 1.49 (colored)
Don't pretend to support ix86's with 16-bit ints by using longs just to ensure 32-bit variables. Doing so mainly bogotified some printf formats. Fixed disorder in md_var.h.
Revision 1.7.2.18 / (download) - annotate - [select for diffs], Tue Jul 7 05:22:46 1998 UTC (13 years, 7 months ago) by gibbs
Branch: RELENG_2_2
CVS Tags: RELENG_2_2_8_RELEASE,
RELENG_2_2_7_RELEASE
Changes since 1.7.2.17: +3 -3
lines
Diff to previous 1.7.2.17 (colored) to branchpoint 1.7 (colored)
asm->__asm inline->__inline
Revision 1.49 / (download) - annotate - [select for diffs], Tue Jun 30 19:41:21 1998 UTC (13 years, 7 months ago) by phk
Branch: MAIN
CVS Tags: PRE_NOBDEV
Changes since 1.48: +2 -2
lines
Diff to previous 1.48 (colored)
Add PSE36 to the bits we know by name.
Revision 1.7.2.17 / (download) - annotate - [select for diffs], Fri May 22 22:18:42 1998 UTC (13 years, 8 months ago) by des
Branch: RELENG_2_2
Changes since 1.7.2.16: +50 -3
lines
Diff to previous 1.7.2.16 (colored) to branchpoint 1.7 (colored)
MFC: precise identification of models within the 586 and 686 families.
Revision 1.48 / (download) - annotate - [select for diffs], Fri May 22 22:15:14 1998 UTC (13 years, 8 months ago) by des
Branch: MAIN
Changes since 1.47: +41 -8
lines
Diff to previous 1.47 (colored)
Use switch instead of if/else chain for 686 model identification. Add precise model identification for 586-family CPUs.
Revision 1.47 / (download) - annotate - [select for diffs], Thu May 21 22:53:24 1998 UTC (13 years, 8 months ago) by des
Branch: MAIN
Changes since 1.46: +16 -2
lines
Diff to previous 1.46 (colored)
Correctly identify the precise CPU model within the 686 family: instead of just printing "Pentium Pro", check the model (cpu_id & 0xf0) and print the appropriate information.
Revision 1.46 / (download) - annotate - [select for diffs], Tue May 19 19:40:45 1998 UTC (13 years, 8 months ago) by peter
Branch: MAIN
Changes since 1.45: +9 -4
lines
Diff to previous 1.45 (colored)
Missing parens caused cpu features not to be printed for cyrix >= M2/MX. Althought the comments say the datasheet doesn't list the device ID registers on the M2/MX, they seem to be there and quite alive. (It's interesting to note that the M2/MX calls itself a 686 class cpu but is missing a heck of a lot of features, including VME, PGE, PSE, etc)
Revision 1.45 / (download) - annotate - [select for diffs], Sun Apr 26 03:18:38 1998 UTC (13 years, 9 months ago) by dyson
Branch: MAIN
Changes since 1.44: +2 -2
lines
Diff to previous 1.44 (colored)
Add the PAT cpuid feature.
Revision 1.44 / (download) - annotate - [select for diffs], Wed Apr 15 17:44:58 1998 UTC (13 years, 10 months ago) by bde
Branch: MAIN
CVS Tags: PRE_DEVFS_SLICE,
POST_DEVFS_SLICE
Changes since 1.43: +3 -3
lines
Diff to previous 1.43 (colored)
Support compiling with `gcc -ansi'.
Revision 1.7.2.16 / (download) - annotate - [select for diffs], Sat Feb 14 13:44:42 1998 UTC (13 years, 11 months ago) by kato
Branch: RELENG_2_2
CVS Tags: RELENG_2_2_6_RELEASE
Changes since 1.7.2.15: +16 -16
lines
Diff to previous 1.7.2.15 (colored) to branchpoint 1.7 (colored)
MFC: revision 1.43 (use rdmsr instead of wrmsr).
Revision 1.43 / (download) - annotate - [select for diffs], Fri Feb 13 09:34:42 1998 UTC (14 years ago) by kato
Branch: MAIN
CVS Tags: PRE_SOFTUPDATE,
POST_SOFTUPDATE
Changes since 1.42: +16 -16
lines
Diff to previous 1.42 (colored)
Use RDMSR instruction instead of WRMSR.
Revision 1.7.2.15 / (download) - annotate - [select for diffs], Wed Feb 4 14:35:55 1998 UTC (14 years ago) by kato
Branch: RELENG_2_2
Changes since 1.7.2.14: +13 -4
lines
Diff to previous 1.7.2.14 (colored) to branchpoint 1.7 (colored)
MFC: revision 1.42 (cpuid probelm of M2 CPU).
Revision 1.42 / (download) - annotate - [select for diffs], Tue Jan 27 08:12:09 1998 UTC (14 years ago) by kato
Branch: MAIN
Changes since 1.41: +13 -4
lines
Diff to previous 1.41 (colored)
Execute cpuid if BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
Revision 1.41 / (download) - annotate - [select for diffs], Sun Jan 25 23:45:33 1998 UTC (14 years ago) by kato
Branch: MAIN
Changes since 1.40: +4 -13
lines
Diff to previous 1.40 (colored)
Undo previous commit. The cpuid symbol has been already used by SMP stuff. Pointed-out by: Manfred Antar <root@mantar.slip.netcom.com>
Revision 1.40 / (download) - annotate - [select for diffs], Sun Jan 25 17:01:31 1998 UTC (14 years ago) by kato
Branch: MAIN
Changes since 1.39: +13 -4
lines
Diff to previous 1.39 (colored)
Execute cpuid if BIOS disables cpuid instruction of Cyrix 6x86MX CPU, and store its result into cpu_id and cpu_feature variables. Tested by: Simon Coggins <chaos@ultra.net.au>
Revision 1.7.2.14 / (download) - annotate - [select for diffs], Sun Jan 25 15:40:28 1998 UTC (14 years ago) by kato
Branch: RELENG_2_2
Changes since 1.7.2.13: +54 -16
lines
Diff to previous 1.7.2.13 (colored) to branchpoint 1.7 (colored)
MFC: fix general protection fault by wrmsr.
Revision 1.39 / (download) - annotate - [select for diffs], Sun Jan 25 12:01:10 1998 UTC (14 years ago) by kato
Branch: MAIN
Changes since 1.38: +54 -16
lines
Diff to previous 1.38 (colored)
Even though BIOS writer's guide recommends cpuid instruction of Cyrix 6x86MX CPU is enabled (BIOS should not disable it), some BIOS disables it via CCR4. In this case, cpu variable becomes CPU_486 and identblue() is called. Because Cyrix 6x86MX has MSR and doesn't have MSR1002, wrmsr instruction generates general protection fault. Tested by: Simon Coggins <chaos@ultra.net.au>
Revision 1.7.2.13 / (download) - annotate - [select for diffs], Sat Jan 3 08:51:29 1998 UTC (14 years, 1 month ago) by obrien
Branch: RELENG_2_2
Changes since 1.7.2.12: +99 -12
lines
Diff to previous 1.7.2.12 (colored) to branchpoint 1.7 (colored)
Merge rev 1.36 of identcpu.c from -CURRENT. Modivation is the new AMD info. Also required merging rev 1.16 of asmacros.h and rev 1.15 of cdefs.h.
Revision 1.38 / (download) - annotate - [select for diffs], Sat Jan 3 05:43:37 1998 UTC (14 years, 1 month ago) by obrien
Branch: MAIN
Changes since 1.37: +3 -3
lines
Diff to previous 1.37 (colored)
AMD calls the PR166 and PR200, models 2 and 3 respectively.
Revision 1.37 / (download) - annotate - [select for diffs], Sat Jan 3 05:36:40 1998 UTC (14 years, 1 month ago) by obrien
Branch: MAIN
Changes since 1.36: +3 -2
lines
Diff to previous 1.36 (colored)
Update AMD URL for CPU recognition docs.
Revision 1.36 / (download) - annotate - [select for diffs], Fri Dec 26 20:41:32 1997 UTC (14 years, 1 month ago) by phk
Branch: MAIN
Changes since 1.35: +5 -5
lines
Diff to previous 1.35 (colored)
Rename "i586_ctr" to "tsc" (both upper and lower case instances). Fix a couple of printfs too. Warning: This changes the names of a couple of kernel options!
Revision 1.7.2.12 / (download) - annotate - [select for diffs], Thu Dec 4 14:36:55 1997 UTC (14 years, 2 months ago) by jkh
Branch: RELENG_2_2
Changes since 1.7.2.11: +3 -3
lines
Diff to previous 1.7.2.11 (colored) to branchpoint 1.7 (colored)
MFC: F00F cleanup.
Revision 1.35 / (download) - annotate - [select for diffs], Thu Dec 4 14:35:38 1997 UTC (14 years, 2 months ago) by jkh
Branch: MAIN
Changes since 1.34: +3 -3
lines
Diff to previous 1.34 (colored)
After consultation with David, change #ifndef NO_F00F_HACK to #if defined(I586_CPU) && !defined(NO_F00F_HACK)
Revision 1.7.2.11 / (download) - annotate - [select for diffs], Wed Dec 3 02:48:25 1997 UTC (14 years, 2 months ago) by sef
Branch: RELENG_2_2
Changes since 1.7.2.10: +13 -1
lines
Diff to previous 1.7.2.10 (colored) to branchpoint 1.7 (colored)
MFC -- Intel Pentium F00F bug workaround. Note that I forgot the reviewer credit in the current log message; also credit to Cy Schubert <cschubert@uumail.gov.bc.ca> for cleaning up my initial patches. Reviewed by: Stephen McKay <syssgm@dtir.gld.gov.au>
Revision 1.34 / (download) - annotate - [select for diffs], Wed Dec 3 02:45:42 1997 UTC (14 years, 2 months ago) by sef
Branch: MAIN
Changes since 1.33: +13 -1
lines
Diff to previous 1.33 (colored)
Work around for the Intel Pentium F00F bug; this is Intel's recommended workaround. Note that this currently eats up two pages extra in the system; this could be alleviated by aligning idt correctly, and then only dealing with that (as opposed to the current method of allocated two pages and copying the IDT table to that, and then setting that to be the IDT table).
Revision 1.7.2.10 / (download) - annotate - [select for diffs], Fri Nov 7 12:56:48 1997 UTC (14 years, 3 months ago) by kato
Branch: RELENG_2_2
Changes since 1.7.2.9: +27 -6
lines
Diff to previous 1.7.2.9 (colored) to branchpoint 1.7 (colored)
MFC: revision 1.32 (MediaGX CPU identification).
Revision 1.33 / (download) - annotate - [select for diffs], Fri Nov 7 08:52:27 1997 UTC (14 years, 3 months ago) by phk
Branch: MAIN
Changes since 1.32: +1 -2
lines
Diff to previous 1.32 (colored)
Remove a bunch of variables which were unused both in GENERIC and LINT. Found by: -Wunused
Revision 1.32 / (download) - annotate - [select for diffs], Thu Nov 6 03:10:28 1997 UTC (14 years, 3 months ago) by kato
Branch: MAIN
Changes since 1.31: +27 -6
lines
Diff to previous 1.31 (colored)
Identify MediaGX CPU correctly. Old MeidaGX CPU and GXm CPU are distinguished. CPU-classes of MeidaGX CPU and GXm CPU are 486-class and 586-class, respectively. PR: 4936
Revision 1.7.2.9 / (download) - annotate - [select for diffs], Wed Nov 5 15:15:00 1997 UTC (14 years, 3 months ago) by kato
Branch: RELENG_2_2
Changes since 1.7.2.8: +2 -2
lines
Diff to previous 1.7.2.8 (colored) to branchpoint 1.7 (colored)
MFC: revision 1.31 (Fix 6x86 recognition).
Revision 1.31 / (download) - annotate - [select for diffs], Wed Nov 5 15:12:44 1997 UTC (14 years, 3 months ago) by kato
Branch: MAIN
Changes since 1.30: +2 -2
lines
Diff to previous 1.30 (colored)
Fix rare 6x86 CPU whose DIR0 = 0x20 - 0x28 case.
Revision 1.30 / (download) - annotate - [select for diffs], Tue Oct 28 11:43:43 1997 UTC (14 years, 3 months ago) by bde
Branch: MAIN
Changes since 1.29: +3 -2
lines
Diff to previous 1.29 (colored)
Don't include <machine/cputypes.h> or declare cputype/class interfaces in <machine/cpu.h>. Moved the declarations to <machine/cputypes.h>. Fixed style bugs in the moved code. Fixed everything that depended on the nested include. Don't include <machine/cpu.h> (in the changed files) unless something in it is used directly.
Revision 1.7.2.8 / (download) - annotate - [select for diffs], Fri Oct 3 14:29:48 1997 UTC (14 years, 4 months ago) by kato
Branch: RELENG_2_2
CVS Tags: RELENG_2_2_5_RELEASE
Changes since 1.7.2.7: +3 -2
lines
Diff to previous 1.7.2.7 (colored) to branchpoint 1.7 (colored)
MFC (revision 1.29; M2 DIR). I consider it is obvious bug fix. If bug remains in 2.2.5 RELEASE, wrong version information for M2 CPU (clock, revision and stepping) will be included in bug reports.
Revision 1.29 / (download) - annotate - [select for diffs], Fri Oct 3 14:23:47 1997 UTC (14 years, 4 months ago) by kato
Branch: MAIN
Changes since 1.28: +3 -2
lines
Diff to previous 1.28 (colored)
Call identifycyrix() when 6x86MX CPU is found. The identifycyrix() function sets cyrix_did. Old code could not display correct variable. Reviewed by: Hideyuki Suzuki <hideyuki@sat.t.u-tokyo.ac.jp>
Revision 1.28 / (download) - annotate - [select for diffs], Sat Sep 20 13:18:48 1997 UTC (14 years, 4 months ago) by phk
Branch: MAIN
Changes since 1.27: +71 -1
lines
Diff to previous 1.27 (colored)
For AMD chips, pick up the long description from the chip if possible. (This is not really a typographical improvement in the case of the K6 it seems, but AMD appearantly want it too look that way). Also if bootverbose, dump some more info about the chip.
Revision 1.7.2.7 / (download) - annotate - [select for diffs], Fri Jul 25 08:34:11 1997 UTC (14 years, 6 months ago) by kato
Branch: RELENG_2_2
Changes since 1.7.2.6: +2 -2
lines
Diff to previous 1.7.2.6 (colored) to branchpoint 1.7 (colored)
MFC (I586 --> I686 for Cyrix 6x86MX CPU).
Revision 1.27 / (download) - annotate - [select for diffs], Thu Jul 24 14:19:23 1997 UTC (14 years, 6 months ago) by kato
Branch: MAIN
Changes since 1.26: +2 -2
lines
Diff to previous 1.26 (colored)
Treat 6x86MX CPU as 686-class CPU instead of 586-class CPU.
Revision 1.26 / (download) - annotate - [select for diffs], Sun Jul 20 08:37:18 1997 UTC (14 years, 6 months ago) by bde
Branch: MAIN
Changes since 1.25: +1 -5
lines
Diff to previous 1.25 (colored)
Removed unused #includes.
Revision 1.7.2.6 / (download) - annotate - [select for diffs], Tue Jun 24 10:03:11 1997 UTC (14 years, 7 months ago) by kato
Branch: RELENG_2_2
Changes since 1.7.2.5: +7 -1
lines
Diff to previous 1.7.2.5 (colored) to branchpoint 1.7 (colored)
YMAFC (revision 1.25; recognize AMD K5 PR166 and PR200 CPUs).
Revision 1.25 / (download) - annotate - [select for diffs], Tue Jun 24 09:45:35 1997 UTC (14 years, 7 months ago) by kato
Branch: MAIN
CVS Tags: WOLLMAN_MBUF,
BP_WOLLMAN_MBUF
Changes since 1.24: +7 -1
lines
Diff to previous 1.24 (colored)
Recognize AMD K5 PR166 and PR200 CPUs.
Revision 1.7.2.5 / (download) - annotate - [select for diffs], Fri Jun 20 10:27:33 1997 UTC (14 years, 7 months ago) by kato
Branch: RELENG_2_2
Changes since 1.7.2.4: +313 -8
lines
Diff to previous 1.7.2.4 (colored) to branchpoint 1.7 (colored)
Merge revised CPU identification and initialization routine from current. Now, Cyrix 6x86 chip is recognized as Cyrix 6x86 chip.
Revision 1.24 / (download) - annotate - [select for diffs], Mon Jun 2 18:55:44 1997 UTC (14 years, 8 months ago) by peter
Branch: MAIN
Changes since 1.23: +19 -3
lines
Diff to previous 1.23 (colored)
Fill in some gaps in the cpuid features list.. bit 10 is the old bit for MTRR (presumably this changed, an older P5 I have has got it, the newer cpus have the new MTRR bit set) bit 11 is SEP (fast syscalls), bit 23 is MMX Fill in the other reserved ones with a stub so that we can see them if they turn up. Obtained from: Intel AP-485 rev.06
Revision 1.23 / (download) - annotate - [select for diffs], Mon Jun 2 08:19:02 1997 UTC (14 years, 8 months ago) by dfr
Branch: MAIN
Changes since 1.22: +2 -2
lines
Diff to previous 1.22 (colored)
Move interrupt handling code from isa.c to a new file. This should make isa.c (slightly) more portable and will make my life developing the really portable version much easier. Reviewed by: peter, fsmp
Revision 1.22 / (download) - annotate - [select for diffs], Sat May 31 08:45:23 1997 UTC (14 years, 8 months ago) by kato
Branch: MAIN
Changes since 1.21: +147 -128
lines
Diff to previous 1.21 (colored)
- Use `6x86MX' instead of `M2'. Cyrix officially use `6x86MX' for the CPU code-named `M2'. - Use the result of cpuid instruction instead of DIR to identify 6x86MX cpu. DIR0 and DIR1 are not documented in the data sheet, and cpuid instruction is enabled at reset time. - Add a function, init_6x86MX() to initialize 6x86MX cpu. It supports CPU_SUSP_HLT and CPU_IORT options. It always sets NC1 (640K - 1M is not cached.), and enables L1 cache in write-back mode. - Fix typo in the comment in identblue().
Revision 1.21 / (download) - annotate - [select for diffs], Fri May 23 06:22:47 1997 UTC (14 years, 8 months ago) by charnier
Branch: MAIN
Changes since 1.20: +2 -2
lines
Diff to previous 1.20 (colored)
typo (Cyirx -> Cyrix).
Revision 1.7.2.4 / (download) - annotate - [select for diffs], Mon May 19 12:59:51 1997 UTC (14 years, 8 months ago) by kato
Branch: RELENG_2_2
Changes since 1.7.2.3: +16 -1
lines
Diff to previous 1.7.2.3 (colored) to branchpoint 1.7 (colored)
YAMFC (revision 1.20; recognize AMD 486 CPUs).
Revision 1.20 / (download) - annotate - [select for diffs], Mon May 19 12:41:35 1997 UTC (14 years, 8 months ago) by kato
Branch: MAIN
Changes since 1.19: +16 -1
lines
Diff to previous 1.19 (colored)
Recognize AMD 486 CPUs.
Revision 1.19 / (download) - annotate - [select for diffs], Mon May 5 14:30:00 1997 UTC (14 years, 9 months ago) by kato
Branch: MAIN
Changes since 1.18: +2 -2
lines
Diff to previous 1.18 (colored)
Use `MediaGX' instead of `Gx86'.
Revision 1.18 / (download) - annotate - [select for diffs], Mon May 5 14:11:09 1997 UTC (14 years, 9 months ago) by kato
Branch: MAIN
Changes since 1.17: +3 -3
lines
Diff to previous 1.17 (colored)
Use `M2' instead of `6x86 with MMX'. Cyrix seems to use `M2' officially.
Revision 1.17 / (download) - annotate - [select for diffs], Sat Apr 26 11:45:07 1997 UTC (14 years, 9 months ago) by peter
Branch: MAIN
CVS Tags: post_smp_merge
Changes since 1.16: +5 -1
lines
Diff to previous 1.16 (colored)
Man the liferafts! Here comes the long awaited SMP -> -current merge! There are various options documented in i386/conf/LINT, there is more to come over the next few days. The kernel should run pretty much "as before" without the options to activate SMP mode. There are a handful of known "loose ends" that need to be fixed, but have been put off since the SMP kernel is in a moderately good condition at the moment. This commit is the result of the tinkering and testing over the last 14 months by many people. A special thanks to Steve Passe for implementing the APIC code!
Revision 1.16 / (download) - annotate - [select for diffs], Sat Apr 26 04:08:45 1997 UTC (14 years, 9 months ago) by kato
Branch: MAIN
CVS Tags: pre_smp_merge
Changes since 1.15: +5 -2
lines
Diff to previous 1.15 (colored)
Add new cpu type, CPU_CY486DX, which shows Cyrix 486S/DX series CPUs, and initialization routine for those CPUs. Tested by: Bob Bishop <rb@gid.co.uk>
Revision 1.15 / (download) - annotate - [select for diffs], Tue Apr 22 06:55:23 1997 UTC (14 years, 9 months ago) by jdp
Branch: MAIN
Changes since 1.14: +5 -3
lines
Diff to previous 1.14 (colored)
Make the necessary changes so that an ELF kernel can be built. I have successfully built, booted, and run a number of different ELF kernel configurations, including GENERIC. LINT also builds and links cleanly, though I have not tried to boot it. The impact on developers is virtually nil, except for two things. All linker sets that might possibly be present in the kernel must be listed in "sys/i386/i386/setdefs.h". And all C symbols that are also referenced from assembly language code must be listed in "sys/i386/include/asnames.h". It so happens that failure to do these things will have no impact on the a.out kernel. But it will break the build of the ELF kernel. The ELF bootloader works, but it is not ready to commit quite yet.
Revision 1.14 / (download) - annotate - [select for diffs], Sat Mar 22 18:51:57 1997 UTC (14 years, 10 months ago) by kato
Branch: MAIN
Changes since 1.13: +290 -7
lines
Diff to previous 1.13 (colored)
Improved CPU identification and initialization routines. This
supports All Cyrix CPUs, IBM Blue Lightning CPU and NexGen (now AMD)
Nx586 CPU, and initialize special registers of Cyrix CPU and msr of
IBM Blue Lightning CPU.
If revision of Cyrix 6x86 CPU < 2.7, CPU cache is enabled in
write-through mode. This can be disabled by kernel configuration
options.
Reviewed by: Bruce Evans <bde@freebsd.org> and
Jordan K. Hubbard <jkh@freebsd.org>
Revision 1.13 / (download) - annotate - [select for diffs], Sat Feb 22 09:32:19 1997 UTC (14 years, 11 months ago) by peter
Branch: MAIN
Changes since 1.12: +1 -1
lines
Diff to previous 1.12 (colored)
Back out part 1 of the MCFH that changed $Id$ to $FreeBSD$. We are not ready for it yet.
Revision 1.7.2.3 / (download) - annotate - [select for diffs], Sun Feb 2 18:47:05 1997 UTC (15 years ago) by joerg
Branch: RELENG_2_2
CVS Tags: RELENG_2_2_2_RELEASE,
RELENG_2_2_1_RELEASE,
RELENG_2_2_0_RELEASE
Changes since 1.7.2.2: +21 -7
lines
Diff to previous 1.7.2.2 (colored) to branchpoint 1.7 (colored)
YAMFC (rev 1.11 & 1.12: identify AMD CPUs)
Revision 1.12 / (download) - annotate - [select for diffs], Fri Jan 24 12:39:11 1997 UTC (15 years ago) by obrien
Branch: MAIN
Changes since 1.11: +8 -6
lines
Diff to previous 1.11 (colored)
KNF style police. Reported by: Bruce Thanks to: Bruce for also providing a diff.
Revision 1.11 / (download) - annotate - [select for diffs], Sun Jan 19 01:56:55 1997 UTC (15 years ago) by obrien
Branch: MAIN
Changes since 1.10: +18 -6
lines
Diff to previous 1.10 (colored)
Add bits to identify AMD K5 and K6 cpu's. Tested only on my AMD K5 PR-133. Bit values for K6 taken from AMD document on how to test such things. 2.2 Candidate.
Revision 1.10 / (download) - annotate - [select for diffs], Tue Jan 14 06:38:47 1997 UTC (15 years, 1 month ago) by jkh
Branch: MAIN
Changes since 1.9: +1 -1
lines
Diff to previous 1.9 (colored)
Make the long-awaited change from $Id$ to $FreeBSD$ This will make a number of things easier in the future, as well as (finally!) avoiding the Id-smashing problem which has plagued developers for so long. Boy, I'm glad we're not using sup anymore. This update would have been insane otherwise.
Revision 1.7.2.2 / (download) - annotate - [select for diffs], Tue Nov 12 13:54:49 1996 UTC (15 years, 3 months ago) by phk
Branch: RELENG_2_2
Changes since 1.7.2.1: +1 -2
lines
Diff to previous 1.7.2.1 (colored) to branchpoint 1.7 (colored)
yamfc
Revision 1.9 / (download) - annotate - [select for diffs], Tue Nov 12 13:36:52 1996 UTC (15 years, 3 months ago) by bde
Branch: MAIN
Changes since 1.8: +1 -2
lines
Diff to previous 1.8 (colored)
Removed #include of "opt_temporary.h". All the temporary options went away, so this header is no longer generated. This change should be in 2.2. The old version shouldn;t have been in 2.2 (blush).
Revision 1.7.2.1 / (download) - annotate - [select for diffs], Tue Nov 12 09:07:46 1996 UTC (15 years, 3 months ago) by phk
Branch: RELENG_2_2
Changes since 1.7: +1 -13
lines
Diff to previous 1.7 (colored)
Mega-merge from -current
Revision 1.8 / (download) - annotate - [select for diffs], Mon Nov 11 20:38:50 1996 UTC (15 years, 3 months ago) by bde
Branch: MAIN
Changes since 1.7: +1 -13
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Diff to previous 1.7 (colored)
Replaced I586_OPTIMIZED_BCOPY and I586_OPTIMIZED_BZERO with boot-time negative-logic flags (flags 0x01 and 0x02 for npx0, defaulting to unset = on). This changes the default from off to on. The options have been in current for several months with no problems reported. Added a boot-time negative-logic flag for the old I5886_FAST_BCOPY option which went away too soon (flag 0x04 for npx0, defaulting to unset = on). Added a boot-time way to set the memory size (iosiz in config, iosize in userconfig for npx0). LINT: Removed old options. Documented npx0's flags and iosiz. options.i386: Removed old options. identcpu.c: Don't set the function pointers here. Setting them has to be delayed until after userconfig has had a chance to disable them and until after a good npx0 has been detected. machdep.c: Use npx0's iosize instead of MAXMEM if it is nonzero. support.s: Added vectors and glue code for copyin() and copyout(). Fixed ifdefs for i586_bzero(). Added ifdefs for i586_bcopy(). npx.c: Set the function pointers here. Clear hw_float when an npx exists but is too broken to use. Restored style from a year or three ago in npxattach().
Revision 1.7 / (download) - annotate - [select for diffs], Wed Oct 9 19:47:15 1996 UTC (15 years, 4 months ago) by bde
Branch: MAIN
CVS Tags: RELENG_2_2_BP
Branch point for: RELENG_2_2
Changes since 1.6: +2 -1
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Diff to previous 1.6 (colored)
Put I*86_CPU defines in opt_cpu.h.
Revision 1.6 / (download) - annotate - [select for diffs], Wed Oct 9 18:30:08 1996 UTC (15 years, 4 months ago) by bde
Branch: MAIN
Changes since 1.5: +16 -4
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Diff to previous 1.5 (colored)
Enable the i586-optimized bcopy if the cpu is a "586" and option I586_OPTIMIZED_BCOPY is configured. Similarly for bzero/I586_OPTIMIZED_BZERO. Fake 586's had better have a hardware FPU with non-broken exception handling (we mask exceptions, but broken exception handling may trap on the instructions that do the masking). I guess this means that the routines won't work on most 386's or FPUless 486's even when they have a h/w FPU.
Revision 1.5 / (download) - annotate - [select for diffs], Fri Sep 6 23:07:02 1996 UTC (15 years, 5 months ago) by phk
Branch: MAIN
Changes since 1.4: +1 -15
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Diff to previous 1.4 (colored)
Remove devconf, it never grew up to be of any use.
Revision 1.4 / (download) - annotate - [select for diffs], Sat Aug 10 08:04:24 1996 UTC (15 years, 6 months ago) by peter
Branch: MAIN
Changes since 1.3: +15 -1
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Diff to previous 1.3 (colored)
Add recognition for the AMD 5x86 CPU models. Submitted by: A JOSEPH KOSHY <koshy@india.hp.com>
Revision 1.3 / (download) - annotate - [select for diffs], Sat Aug 10 06:35:35 1996 UTC (15 years, 6 months ago) by peter
Branch: MAIN
Changes since 1.2: +5 -3
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Diff to previous 1.2 (colored)
Trivial cosmetic tweak to make the i[56]86 CPU MHz reprting round to the nearest .01 Mhz rather than simply truncating it downwards. This hack makes this 89.999928 Mhz clock correctly round to the closer 90.00-MHz rather than 89.99-MHz: > i586 clock: 89999928 Hz, i8254 clock: 1193152 Hz > CPU: Pentium (90.00-MHz 586-class CPU)
Revision 1.2 / (download) - annotate - [select for diffs], Fri Aug 2 21:15:47 1996 UTC (15 years, 6 months ago) by bde
Branch: MAIN
Changes since 1.1: +3 -5
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Diff to previous 1.1 (colored)
Eliminated i586_ctr_rate. Use i586_ctr_freq instead.
Revision 1.1 / (download) - annotate - [select for diffs], Mon Jul 8 19:44:38 1996 UTC (15 years, 7 months ago) by wollman
Branch: MAIN
Fix something that's been bugging me for a long time: move the CPU type identification code out of machdep.c and into a new file of its own. Hopefully other grot can be moved out of machdep.c as well (by other people) into more descriptively-named files.